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part number 440SPE revision 1.23 - sept 21, 2006 amcc proprietary 1 powerpc 440SPE embedded processor preliminary data sheet features ?powerpc ? 440 processor core operating up to 667 mhz with 32kb i- and d-caches (with parity checking) ? on-chip 256kb sram configurable as l2 cache or ethernet packet/code store memory ? selectable processor vs bus clock ratios (refer to the clocking chapter in the ppc440SPE embedded processor user?s manual for details) ? support up to 16 gb (4 chip selects) of 64-bit/32- bit sdram with ecc ddr i 266-333-400 ddr ii 400-533-667 ? three pci-express serial interfaces: one 8 lanes and two 4 lanes - 2.5gb/s per lane root and endpoint support. opaque bridge ? one 64-bit ddr pci-x interfaces up to 133 mhz (ddr 266) with support for conventional pci ? optional: high throughput raid 6 hardware acceleration, performs xor and galois field p & q parity computations, supports up to 255 drives ? optional:16 programmable galois field polynomials including 14d and 11d ? xor accelerator with dma controller ? i2o messaging with two dma controllers ? external peripheral bus (16-bit data, 27-bit address) for up to three devices; bank0=16 mb, bank1 and bank2=128 mb each ? one ethernet 10/100/1000mbps half- or full- duplex interface. operational modes supported are mii and gmii. ? programmable interrupt controller supports interrupts from a variety of sources. ? programmable general purpose timers (gpt) ? three serial ports (16750 compatible uart) ? two iic interfaces ? general purpose i/o (gpio) interface available ? jtag interface for board level testing ? processor can boot from pci memory description designed specifically to address high-end embedded applications for storage, the powerpc 440SPE (ppc440SPE) provides a high-performance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation. this chip contains a high-performance risc processor core, a ddr1/ddr2 sdram controller, configurable 256kb sram to be used as l2 cache or software-controlled on-chip memory, three pci- express interfaces, one ddr pci-x bus interface, a 1gbps ethernet interface, an i2o/dma controller, control for external rom and peripherals, optional raid 6 acceleration, an xor dma unit, serial ports, iic interfaces, and general purpose i/o. technology: cmos cu-11, 0.13mm package: 27mm, 675-ball, 1mm pitch, flip chip- plastic ball grid array (fc-pbga) power (estimated): less than 14w @533mhz supply voltages required: 3.3v, 2.5v, 1.8v, 1.5v
powerpc 440SPE embedded processor 2 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet contents ordering and pvr information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ppc440SPE functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 address maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 powerpc 440 processor core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 internal buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 on-chip sram/l2 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 pci express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ddr pci-x interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ddr1/ddr2 sdram memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 external peripheral bus controller (ebc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ethernet controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 i2o/dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 optional raid 5 and raid 6 acceleration hard ware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 xor/dma2 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 serial port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 iic bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 general purpose timers (gpt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 general purpose io (gpio) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 universal interrupt controller (uic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 27mm, 675-ball fc-pbga core package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 signal lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 clock test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 clock timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 spread spectrum clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 input/output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 input setup and hold waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 output delay and hold timing wa veform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ddr sdram i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ddr sdram write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ddr sdram read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 serial bootstrap rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 3 preliminary data sheet figures figure 1. order part number ke y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. ppc440SPE functional block diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. 27mm, 675-ball fc-pbga core package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4. clock timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 5. input setup and hold waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 6. output delay and hold timing wa veform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 7. ddr sdram signal termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 8. ddr sdram write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 9. ddr sdram read data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 10. ddr sdram memory data and dqs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 11. ddr sdram read cycle timing?example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 tables table 1. system memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. dcr address map (4kb of device configuration registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. signals listed alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. signals listed by ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 5. pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 6. signal functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 8. package thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 9. recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 10. input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 11. dc power supply loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 12. clocking specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 13. peripheral interface clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 14. i/o specifications?all speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 15. i/o specifications?667mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 16. ddr sdram output driver specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 17. ddr sdram read and write i/o timi ng?tsa and tha . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 18. ddr sdram clock to write dqs timing?t ds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 19. ddr sdram write data to dqs timing?tsd and thd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 20. ddr sdram i/o read timing?t sd and t hd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 21. strapping pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
powerpc 440SPE embedded processor 4 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet ordering and pvr information for information about the availability of the following parts, contact your local sales office. the mo st current version of the 440SPE is revision b. the part numbers for 440SPE revision b are shown in the following figures. each part number contains a revision code. this is the die mask revision number and is included in the part number for identification purposes only. the pvr (processor version register) and the jtag id register are software accessible (read-only) and contain information that uniquely identifies the part. see the ppc440SPE embedded processor user?s manual for details about accessing these registers. note: raid-enabled versions (product feature = r) require a raid key license. figure 1. order part number key the part numbers for 440SPE revision a are shown in the following figure. product name order part number (see notes 1-5) package rev level pvr value jtag id ppc440SPE ppc440SPE-xpbfffc 27mm, 675 fc-pbga b 0x53421891 0x14538049 notes: 1. x = product feature a = raid6 not enabled (rev level b only) r = raid6 enabled (rev level b only) 2. p = module package type g = leaded fc-pbga n = lead free fc-pgba (rohs compliant) 3. b = chip revision level b (2.0) 4. fff = processor frequency 533 = 533mhz 667 = 667mhz 5. c = case temperature range of 0c to +95c product name order part number processor frequency package rev level pvr value jtag id ppc440SPE ppc440SPE-3ga533c 533mhz 27mm, 675 fc-pbga a 0x53421890 0x14538049 ppc440SPE ppc440SPE-3ga667c 667mhz 27mm, 675 fc-pbga a 0x53421890 0x14538049 ppc440SPE-rnb667c package product feature case temperature range revision level processor speed amcc part number note: the example part number above is a raid6-enabled, lead-free package, at chip revision level b, at pci express core revision level 1.1, capable of running at 667 mhz, and is shipped in tray packaging.
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 5 preliminary data sheet ppc440SPE functional block diagram figure 2. ppc440SPE functional block diagram the ppc440SPE is a system on a chip (soc) designed around the ibm coreconnect bus ? architecture. implemented with the crossbar option, the coreconnect buses provide: ? two master plb bus 128-bit data 64-bit address plb interfaces up to 166.66mh z, 2.6gb/s on both the read and write data path (10.6 gb/s total) ? 32-bit opb interfaces up to 83.33mhz for a maximum throughput of 333mb/s processor core dcr bus 32kb on-chip peripheral bus (opb) gpio iic uart bridge external clock, control, reset power mgmt jtag timers mmu opb interrupt controller universal i-cache 32kb d-cache xor/dma ppc440 pci-express x2 x3 mal ethernet dcrs gp timers 256 kb low latency (ll) segment high bandwidth (hb) segment processor local bus (plb) trace arb plb i2o/dma memory pci-e0 pci-e1 pci-e2 mii, gmii queue ddr pci-x 4 lanes 8 lanes 4 lanes irq handler pci-e bus controller (ebc) 10/100/ 1000 controller (dma0 and dma1) accelerator unit (dma2) registers 64-bit 64+8 16 16 irqs ddr 1 and 2 sdram cntl l2 cache/sram mac
powerpc 440SPE embedded processor 6 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet address maps the ppc440SPE incorporates two address maps. the first is a fixed processor system memory address map. this address map defines the possible contents of various proc essor accessible address regions. the second address map identifies the system device configuration registers (d crs). dcrs are accessed by software running on the ppc440SPE processor through the use of mtdcr and mfdcr instructions. table 1. system memory address map (sheet 1 of 2) function sub function start address end address size local memory (ll) 1 ddr sdram 0000 0000 0000 0000 0000 0003 ffff ffff 16gb sram 0000 0004 0000 0000 0000 0004 0003 ffff 256kb reserved 0000 0004 0004 0000 0000 0004 000f ffff internal plb interfaces (ll) i2o registers 0000 0004 0010 0000 0000 0004 0010 00ff 256b dma 0 registers 0000 0004 0010 0100 0000 0004 0010 01ff 256b dma 1 registers 0000 0004 0010 0200 0000 0004 0010 02ff 256b i20/dma buffers 0000 0004 0010 0300 0000 0004 0010 0fff 3.25k b reserved 0000 0004 0010 1000 0000 0004 001f ffff xor/dma2 0000 0004 0020 0000 0000 0004 0020 03ff 1kb reserved 0000 0004 0020 0400 0000 0004 002f ffff pci express interrupt handler 0000 0004 0030 0000 0000 0004 0030 00ff 256b reserved 0000 0004 0030 0100 0000 0004 dfff ffff internal opb peripherals (ll) ebc memory 6 0000 0004 e000 0000 0000 0004 efff ffff 256mb reserved 0000 0004 f000 0000 0000 0004 f000 01ff uart0 0000 0004 f000 0200 0000 0004 f000 0207 8b reserved 0000 0004 f000 0208 0000 0004 f000 02ff uart1 0000 0004 f000 0300 0000 0004 f000 0307 8b reserved 0000 0004 f000 0308 0000 0004 f000 03ff iic0 0000 0004 f000 0400 0000 0004 f000 041f 32b reserved 0000 0004 f000 0420 0000 0004 f000 04ff iic1 0000 0004 f000 0500 0000 0004 f000 051f 32b reserved 0000 0004 f000 0520 0000 0004 f000 05ff uart2 0000 0004 f000 0600 0000 0004 f000 0607 8b reserved 0000 0004 f000 0608 0000 0004 f000 06ff 248b gpio controller registers 0000 0004 f000 0700 0000 0004 f000 077f 128b reserved 0000 0004 f000 0780 0000 0004 f000 07ff ethernet controller registers 0000 0004 f000 0800 0000 0004 f000 08ff 256b reserved 0000 0004 f000 0900 0000 0004 f000 09ff
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 7 preliminary data sheet general purpose timers 0000 0004 f000 0a00 0000 0004 f000 0b3f 320b reserved 0000 0004 f000 0b40 0000 0004 feff ffff boot rom 2, 3 ebc bank0 0000 0004 ff00 0000 0000 0004 ffff ffff 16mb reserved 0000 0005 0000 0000 0000 0007 ffff ffff local memory alias (hb) aliased ddr sdram 0000 0008 0000 0000 0000 000b ffff ffff 16gb pci space (hb) reserved 0000 000c 0000 0000 0000 000c 07ff ffff pcix0 i/o 0000 000c 0800 0000 0000 000c 0800 ffff 64kb reserved 0000 000c 0801 0000 0000 000c 0ebf ffff pcix0 addressing configuration regs 0000 000c 0ec0 0000 0000 000c 0ec0 0007 8b reserved 0000 000c 0ec0 0008 0000 000c 0ec7 ffff pcix0 core configuration regs 0000 000c 0ec8 0000 0000 000c 0ec8 0fff 4kb reserved 0000 000c 0ec8 1000 0000 000c 0ec8 10ff pcix0 simple message passing 0000 000c 0ec8 1100 0000 000c 0ec8 11ff 256b reserved 0000 000c 0ec8 1200 0000 000c 0ecf ffff pcix0 special cycle 0000 000c 0ed0 0000 0000 000c 0edf ffff 1mb reserved 0000 000c 0ee0 0000 0000 000c 0fff ffff pci memory (pci-express & pci-x) 0000 000c 1000 0000 0000 000c feff ffff 3.8gb pci-x ddr boot rom (pci memory 0000 000c ff00 0000 0000 000c ffff ffff 16mb pci memory (pci-express & pci-x) 0000 000d 0000 0000 0000 000f ffff ffff 12gb reserved 4 0000 0010 0000 0000 0fff ffff ffff ffff reserved 5 1000 0000 0000 0000 1fff ffff ffff ffff pci core space (hb) pci memory (pci-express & pci-x) 2000 0000 0000 0000 ffff ffff ffff ffff notes: 1. ddr sdram and on-chip sram can be located anywhere in the local memory area of the memory map. 2. the boot rom and expansion rom areas of the memory map ar e intended for use by rom or fl ash-type devices. while locating volatile ddr sdram and sram in this region is supported, use of these regions for this purpose is not recommended. 3. when the optional boot from pci-x memory is selected, the pci-x boot rom address space begins at c ff00 0000 (16 mb). 4. never decoded. 5. unpredictable results on read and write operations. 6. accessed by means of ebc peripheral bank configuration registers. table 1. system memory address map (sheet 2 of 2) function sub function start address end address size
powerpc 440SPE embedded processor 8 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet table 2. dcr address map (4kb of device configuration registers) function start address end address size total dcr address space 1 000 3ff 1kw (4kb) 1 by function: reserved 000 00b 12w clocking power on reset 00c 00d 2w system dcrs 00e 00f 2w memory controller 010 011 2w external bus controller 012 013 2w reserved 014 01f 12w sram 020 02f 16w l2 controller 030 03f 16w memory queue 040 05f 32w i2o, dma0 & dma1 060 07f 32w plb 080 08f 16w plb to opb bridge out 090 09f 16w reserved 0a0 0af 16w reserved 0b2 0bf 14w interrupt controller 0 0c0 0cf 16w interrupt controller 1 0d0 0df 16w interrupt controller 2 0e0 0ef 16w interrupt controller 3 0f0 0ff 16w pci-express 0 100 11f 32w pci-express 1 120 13f 32w pci-express 2 140 15f 32w power management 160 167 8w reserved 168 17f 24w ethernet mal 180 1ff 128w reserved 200 3ff 512w notes: 1. dcr address space is addressable with up to 10 bits (1024 or 1k unique addresses). each unique address represents a sin- gle 32-bit (word) register. one kw (1024w) equals 4kb (4096 bytes).
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 9 preliminary data sheet powerpc 440 processor core the powerpc 440 processor core is designed for high-end applications such as raid controllers, san, iscsi, routers, switches, printers, set-top bo xes, and so on. it is the first processor core to implement the book e powerpc embedded architecture and uses the 128-bit ve rsion of ibm?s on-chip coreconnect bus architecture. features include: ? up to 800 mhz operation ? powerpc book e architecture ? 32kb i-cache, 32kb d-cache ? parity on data and tag address - checking of parity with error injection ? three logical regions in d-cache: locked, transient, and normal ? d-cache full-line flush capability ? 41-bit virtual address, 36-bit (64gb) physical address ? superscalar, out-of-order execution ? seven-stage pipeline ? three execution pipelines ? dynamic branch prediction ? memory management unit ? 64-entry, full associative, unified tlb with parity ? separate instruction and data micro-tlbs ? storage attributes for write-through, cache- inhibited, guarded, and big or little endian ? debug facilities ? multiple instruction and data range breakpoints ? data value compare ? single step, branch, and trap events ? non-invasive real-time trace interface ? 24 dsp instructions ? single cycle multiply and multiply-accumulate ? 32 x 32 integer multiply internal buses the powerpc 440SPE features three ibm standard on-chip buses: the processor local bus (plb), the on-chip peripheral bus (opb), and the device control register bus (dcr). the high performance, high bandwidth cores such as the powerpc 440 processor core, the ddr sd ram memory controller, the pci express and the ddr pci-x bridges connect to the plb. the opb hosts lower da ta rate peripherals. the daisy-chained dcr provides a lower bandwidth path for passing status and control information between the processor core and the other on-chip cores. the plb has a crossbar arbiter that supports data tran sfer between the plb master and two slave segments identified as the low latency (ll) and high bandwidth (h b) segments. the ll segment allows plb masters cpu and i2o, that are adversely affected by latency, to co mmunicate with slave devices wit h minimal latency. the hb segment allows plb masters dma, xo r, pci and pci express to exchange large blocks of data with sdram, pci and pci express without interfering with the low latency plb masters. bus features include: ?plb ? 128-bit implementation of the plb architecture ? separate and simultaneous read and write data paths ? 64-bit address ? simultaneous control, address, and data phases ? four levels of pipelining ? byte enable capability suppor ting unaligned transfers ? 32- and 64-byte burst transfers
powerpc 440SPE embedded processor 10 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet ? 166mhz, maximum 5.2gb/s (simultaneous read and write) ? processor vs bus clock ratios of n:1 and n:2 ?opb ? dynamic bus sizing: 32, 16, and 8-bit data path ? 32-bit address ? 83.33mhz, maximum 333mb/s ? dcr ? register control bus ? 32-bit data path ? 10-bit address on-chip sram/l2 cache features include: ? four banks of 64kb each for a total of 256kb ? configurable as either l2 cache or sram ? memory cycles supported: ? single beat read and write, 1 to 16 bytes ? quadword read and write burst for 12-bit master ? guarded memory accesses on 4kb boundaries ? sustainable 2.6gb/s peak bandwidth at 166mhz ? use as an l2 cache improves proces sor performance and reduces the plb load ? cache coherency maintained by a hardware snoop mechanism on the low latency (ll) plb or by software ? data array and tag array parity ? unified data and instruction cache ? four-way set associative ? 36-bit addressing ? full lru replacement algorithm ? write through, look aside ? use as ethernet packet store a llows ethernet packets to be held for processing by the ethernet core pci express features include: ? three independent pci express interfaces ? one 8 lanes ?two 4 lanes ? 2.5 gb/sec full duplex per lane ? compliant with pci express base specification 1.0a ? each pci express port can be end point or root complex. (upstream & downstream) ? applications compliant with msi rules are limited to one end point port per ppc440SPE ? pci-express to pci-express opaque (non-transparent) bridge ? power management ? supports one virtual channel (vc0) no traffic class (tc) filtering ? maximum payload block size 512 bytes ? supports up to 1024 byte maximum read request size ? requests supported: ? up to 4 posted outbound write r equests (memory and messages) ? up to 4 posted inbound write requests ? up to 4 outbound read requests outstanding on pci express ? up to 4 inbound read requests outstanding on pci express ? outbound i/o request as a pci express root port ? inbound i/o request as a pci express end point
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 11 preliminary data sheet ? buffering in each pci express port for the following transaction types: ? 4k byte replay buffer: up to 8 in flight transactions ? 2k bytes for outbound posted writes ? 8k bytes for outbound reads completion ? 2k prefetch request from first i2o/dma plb master ? 1k prefetch request from 2nd i2o/dma plb master ? 1k prefetch request from first pcie 4x links ? 1k prefetch request from 2nd pcie 4x links ? 256 byte from the ppc440 ? 2k bytes for inbound posted writes ? 2k bytes for inbound reads completion ? parity checking on each buffer ? pom programmable outbound memory regions: 3 memory , 1 i/o, 1 message, 1 config, 1 internal regs ? pim programmable inbound memory region s: 4 memory, 1 i/o, 1 expansion rom ? intx interrupts support (pci legacy): ? up to 4 intx termination for root ports. a/b/c/d interrupts are wired to the uic ? a/b/c/d intx types generation for endpoints ? msi - message signaled interrupts ? msi generation for end point ? msi termination for root ports ? msi_x termination for root ports ddr pci-x interface the ddr pci-x interface allows connection of pci an d pci-x devices to the powerpc processor and local memory. the pci-x interface supports 64-bit pci-x bus in ddr mode 2. it can be configured for either host or adapter mode. pci 32/64-bit legacy mode, compatib le with pci version 2.3, is also supported. features include: ?pci-x 2.0 ? split transactions ? frequency to 266mhz ? 32- and 64-bit address/data bus ? ecc supported for 266mhz mode 2 only ? pci 2.3 backwar d compatibility ? frequency to 66mhz ? 32- and 64-bit bus ? can be the pci host bus bridge or an adapter device pci interface ? optional pci arbitration function with pci and pci-x mode 1, supporting up to four external devices, that can be disabled for use with an external arbiter ? support for plb-based (exter nal to plb?pci-x bridge) i2o ? support for message signaled interrupts (msi) on both in- and out-bound interrupts ? simple message passing capability ? asynchronous to the plb ? pci power management version 1.1 ? pci arbitration function with pci-x mode 2 support (optional) ? pci register set addressable both from on-chip processor and pci device sides ? ability to boot from pci-x bus memory ? error tracking/status ? supports initiation of transfer to the following address spaces: ? single beat i/o reads and writes ? single beat and burst memory reads and writes ? single beat configuration reads and writes (type 0 and type 1) ? single beat special cycles
powerpc 440SPE embedded processor 12 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet ? pci-x initialization sequence suppor t (frequency & mode determination) ? support for unexpected split completions ? outbound transaction split discard timers ? vital product data (vpd) support ? pci-x to pci-express opaque bridge ddr1/ddr2 sdram memory controller the ddr2 sdram memory controller supports industry standard 184-pin dimms, so -dimms, and other discrete devices. global memory timings, address and bank sizes, and memory addressing modes are programmable. the ddr2 sdram controller interfaces to the plb through a memory queue (mq) function that includes six high- speed 1kb fifo buffers. features include: ? registered and non-registered industry standard dimms ? ddr2 400/667 support ? 64-and 32-bit memory interfaces with optional 8-bit ecc (sec/ded) ? 5.32gb/s peak bandwidth for the 64-bit interface ? 2.66gb/s peak bandwidth for the 32-bit interface ? four chip (bank) select signals supporting 4 external banks ? cas latencies of 2, 3, 4, 5, 6, and 7 supported ? page mode accesses (up to 32 open pages) with configurable paging policy ? look-ahead request queue with programmable depth of four commands. ? optional optimized command scheduling (activate/precharge non- conflicting banks while accessing the current bank) ? up to 16gb in four external banks ? up to 6 memclkout signals for high loading unbuffered dimms . ? programmable address mapping and timing ? hardware and software initiated self-refresh ? sync dram configuration by means of mode register and extended mode register set commands ? power management (self-refresh, suspend, sleep) ? low latency & high bandwidth plb ports ? selectable plb read response (immediate or deferred) ? programmable low latency & high bandwidth arbitration schemes ? high bandwidth port has four 1kb read buffers and two 1kb write buffers ? low latency port has four 128b read buffers and two 128b write buffers external peripheral bus controller (ebc) features include: ? support boot rom on bank 0; pr ogrammable size 2, 4, 8,16 mb ? up to three rom, eprom, sram, flash memory, and slave peripherals supported ? burst and non-burst devices ? 16 or 8-bit data bus ? 27-bit address, 128mb address space for banks 1 & 2 ? peripheral device pacing with external ?ready? ? latch data on ready, synchronous or asynchronous ? programmable access timing per device ? 256 wait states for non-burst ? 32 burst wait states for first access and up to 8 wait states for subsequent accesses ? programmable cson, csoff relative to address ? programmable oeon, weon, weoff (1 to 4 clock cycles) relative to cs ? programmable address mapping
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 13 preliminary data sheet ethernet controller interface the ethernet support interfaces to the physical la yer, but the phy is not included on the chip. features include: ? one 10/100/1000 interface running in full- and half-duplex modes ? one full media independent interface (mii) with 4-bit parallel data transfer ? one gigabit media independent interface (gmii) i2o/dma controller the i20/dma controller provides suppo rt for i20 messaging and two dma controllers (dma0 and dma1). i2o manages message frame address (mfa) fifos or queues in memory in response to i2o register reads and writes and transfers message frames. the dmas provide normal memory access support to ease the cpu burden. i2o features include: ? i2o pull- and push-messaging methods ? dynamic message frame size ? programmable fifo size (4096 64-bit mfas maximum) ? 64-bit and 32-bit mfa sizes ? three interrupt gathering methods ? registered mfa prefetch and posting ? 32-bit inbound and outbound doorbell registers ? four 32-bit scratch pad registers dma features include: ? programmable command pointer fifo and completion fifo size (up to 2048 dma operations queued) ? 512-byte buffering ? simultaneous fill and drain (plb read/write pipelining) ? any source plb address to any destination address ? no memory alignment restrictio ns on source or destination ? 32-byte command descriptor block ? maximum transfer size of 16mb ? 64-bit addressing ? 1kb buffering (dma1 only) ? prefetch indicators for pci-x buffer management (dma1 only) optional raid 5 and raid 6 acceleration hardware the 440SPE provides integrated acceleration hardware that implements high throughput raid 5 and raid 6 algorithms to compute the single parity p for raid 5, and dual parity p & q for raid 6. raid 5 is used to recover data in the case of a single disk drive failure, and raid 6 provides for data recovery if two disk drives fail. the 440SPE offers a choice of two xor engines for comput ing the p parity. the first choice is available with the xor/dma2 acceleration unit and is used for raid 5. th e second choice for xor parity computation, along with the raid 6 galois field gf(2 8 )-based polynomial computations, resides in side the memory queue functional block of the memory controller unit. the galois field polynomia l used with the 440SPE is programmable and can be one of sixteen available irreducible polynomials, including 14d and 11d. the raid 5 and raid 6 parity computations performed in the memory queue are assisted by the two-channel dma engine of the i2o/dma controller unit, designated as dma0 and dma1. the raid acceleration hardware also provides various alternatives fo r balancing load and performance, depe nding on customer-specific application firmware. the two-way crossbar bus architecture can pe rform data read and write op erations simultaneously, resulting in extremely high throughput. raid 6 capability is available only with the raid-enabled part numbers (ppc440SPE-rpb fffc) as indicated in the ordering information section of this data sheet.
powerpc 440SPE embedded processor 14 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet for more information about the raid 6 implementation, description, and configur ation of the acceleration hardware, refer to the following amcc documents: ? powerpc 440sp/440SPE raid support application note ? powerpc 440SPE raid addendum to the user?s manual xor/dma2 controller the xor/dma2 controller performs the xor functions neede d to support raid 5 applications including parity generation and check functions used ac ross data stripes in a raid 5 system. ? computes a bit-wise xor on up to 16 data str eams with result stored in designated target ? performs xor check on up to 16 data streams ? driven by a linked list command bloc k structure specifying control info rmation, source operands, target operand, status information, and link ? source and target streams may reside anywhere in plb address space. ? provides completion status per command block to be handled by software at a later time ? 96-byte and 160-byte command block formats are supported ? no memory alignment restrictions on operands or target ? internal register arrays and data buffers are parity protected ? can be used as a dma controller (dma2) with single source and target addresses ? plb master interface ? plb slave port used as control interface for r eading and writing control and status information serial port the serial port is compatible with the ns ? 16570 uart interface. features include: ? one 8-pin, one 4-pin, and one 2-pin interfaces are provided ? selectable internal or external serial clock to allow wide range of baud rates ? register compatibility with 16750 register set ? complete status reporting capability ? fully programmable serial-i nterface characteristics iic bus interface features include: ? two iic interfaces provided ? support for philips ? semiconductors i 2 c specification, dated 1995 ? operation at 100khz or 400khz ?8-bit data ? 10- or 7-bit address ? slave transmitter and receiver ? master transmitter and receiver ? multiple bus masters ? supports fixed v dd iic interface ? two independent 4 x 1 byte data buffers ? twelve memory-mapped, fully prog rammable configuration registers ? one programmable interrupt request signal ? full management of all iic bus protocols ? programmable error recovery ? port 0 supports serial bootstrap rom with defa ult override parameters at initialization
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 15 preliminary data sheet general purpose timers (gpt) provides a time base counter and system timers ad ditional to those defined in the processor core. ? 32-bit time base counter driven by the opb bus clock ? seven 32-bit compare timers general purpose io (gpio) controller ? controller functions and gpio registers are progra mmed and accessed by means of memory-mapped opb bus master accesses. ? the 32 gpios are pin-shared with other functions. dcrs control whether a particular pin that has gpio capabilities acts as a gpio or is used for ano ther purpose. ? each gpio output is a separately programmable tri-state driver (pull-up, pull-down, or open-drain). universal interrupt controller (uic) four cascaded universal interrupt controllers (uic) proc ess internal on-chip and external processor interrupts. note: processor specific interrupts (for exampl e, page faults) do not use uic resources. features include: ? 16 external interrupts ? 101 internal interrupts ? edge-triggered or level-sensitive ? positive- or negative-active ? non-critical or critical interrupt to the on-chip processor core ? programmable interrupt priority ordering ? programmable critical interrupt ve ctor for faster vector processing jtag features include: ? ieee 1149.1 test access port ? ibm riscwatch debugger support ? jtag boundary scan description language (bsdl)
powerpc 440SPE embedded processor 16 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet figure 3. 27mm, 675-ball fc-pbga core package top view bottom view note: all dimensions are in mm. 01 03 05 07 09 11 13 15 17 19 02 04 06 08 10 12 14 16 18 21 23 20 22 24 a b c d e f g h j k l m aa n p r t u v w y ab ac ad 27.0 0.2 1.00 typ 27.0 0.2 3.22 max 0.5 min 0.6 0.1 solderball x 675 25 26 af ae lid a1 corner 24 ad a 1 ppc440SPE xpbfffc part number aaaaaaaa lot number ?
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 17 preliminary data sheet signal lists this section contains two tables that list external signals. table 3 lists all the external signals in alphabetical or der and shows the ball (pin) number on which the signal appears. multiplexed signals are shown wi th the default signal (following reset) not in brackets and the alternate signal(s) in brackets. in table 3, multiplexed pins that have no internal signal connected after reset are marked high z. multiplexed signals appear alphabetically multiple times in the list?once for each signal name on the ball. the page number listed gives the page in ?signal functional description? on page 50 where the signals in the indicated interface group begin. table 4 on page 42 lists all the external signals in order by ball (pin) number. signal list?alphabetic order table 3. signals listed alph abetically (sheet 1 of 25) signal name ball interface group page ba0 ae22 ddr sdram 52 ba1 ad21 ba2 ae21 banksel0 ad20 banksel1 y18 banksel2 y19 banksel3 w17 cas ab22 clken0 y21 clken1 aa22 clken2 ae25 clken3 af25 dm0 ad25 ddr sdram 52 dm1 v20 dm2 v25 dm3 t25 dm4 j26 dm5 g22 dm6 f24 dm7 c23 dm8 m19
powerpc 440SPE embedded processor 18 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet dqs0 aa23 ddr sdram 52 dqs0 aa24 dqs1 u21 dqs1 t19 dqs2 w23 dqs2 w24 dqs3 p24 dqs3 p25 dqs4 m22 dqs4 l22 dqs5 g25 dqs5 h25 dqs6 e22 dqs6 f22 dqs7 b25 dqs7 c25 dqs8 p21 dqs8 r21 ecc0 r19 ecc1 r20 ecc2 m20 ecc3 p18 ecc4 p19 ecc5 n19 ecc6 n21 ecc7 n18 table 3. signals listed alph abetically (sheet 2 of 25) signal name ball interface group page
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 19 preliminary data sheet emccd h05 ethernet 53 emccrs d03 emcgtxclk j08 emcmdclk f03 emcmdio b02 emcrefclk h07 emcrxclk b01 emcrxd0 l06 emcrxd1 j02 emcrxd2 g03 emcrxd3 h02 emcrxd4 h03 emcrxd5 l04 emcrxd6 m07 emcrxd7 f05 emcrxdv j06 emcrxerr f04 emctxclk c02 emctxd0 c03 emctxd1 g06 emctxd2 j07 emctxd3 a05 emctxd4 e03 emctxd5 c05 emctxd6 e01 emctxd7 b10 emctxen c01 emctxerr d02 extreset b11 system 55 gnd a04 power 56 gnd a10 gnd a17 gnd a23 gnd d01 table 3. signals listed alph abetically (sheet 3 of 25) signal name ball interface group page
powerpc 440SPE embedded processor 20 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet gnd d07 gnd d13 gnd d14 gnd d20 gnd d26 gnd g04 gnd g10 gnd g17 gnd g23 gnd j09 gnd j12 gnd j15 gnd j18 gnd k01 gnd k07 gnd k10 gnd k12 gnd k15 gnd k17 gnd k20 gnd k26 gnd l11 gnd l13 gnd l14 gnd l16 table 3. signals listed alph abetically (sheet 4 of 25) signal name ball interface group page
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 21 preliminary data sheet gnd m09 power 56 gnd m10 gnd m12 gnd m15 gnd m17 gnd m18 gnd n04 gnd n11 gnd n13 gnd n14 gnd n16 gnd n23 gnd p04 gnd p11 gnd p13 gnd p14 gnd p16 gnd p23 gnd r09 gnd r10 gnd r12 gnd r15 gnd r17 gnd r18 gnd t11 gnd t13 gnd t14 gnd t16 gnd u01 gnd u07 table 3. signals listed alph abetically (sheet 5 of 25) signal name ball interface group page
powerpc 440SPE embedded processor 22 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet gnd u12 power 56 gnd u15 gnd u17 gnd u20 gnd u26 gnd v09 gnd v12 gnd v15 gnd v18 gnd y04 gnd y10 gnd y17 gnd y23 gnd ac01 gnd ac07 gnd ac13 gnd ac14 gnd ac20 gnd ac26 gnd af04 gnd af10 gnd af17 gnd af23 [gpio00] [trcclk] high z l01 gpio peripherals note: trace can be enabled at reset by setting sdr0_sdstp1[dbg] (bit 27) to 1 in the serial bootstrap rom. 55 [gpio01] [trcbs0] high z h01 [gpio02] [trcbs1] high z f01 [gpio03] [trcbs2] high z l02 [gpio04] [trces0] high z k03 [gpio05] [trces1] high z g02 [gpio06] [trces2] high z m05 [gpio07] [trces3] high z f02 [gpio08] [teces4] high z j03 [gpio09] [trcts0] high z h04 [gpio10] [trcts1] high z j05 table 3. signals listed alph abetically (sheet 6 of 25) signal name ball interface group page
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 23 preliminary data sheet [gpio11] [trcts2] high z g05 gpio peripherals 55 [gpio12] [trcts3] high z l05 [gpio13] [trcts4] high z j04 [gpio14] [trcts5] high z k06 [gpio15] [trcts6] high z h06 [gpio16] irq0 l08 [gpio17] irq1 m06 [gpio18] irq2 m08 [gpio19] irq3 e02 [gpio20] irq4 e04 [gpio21] irq5 h09 [gpio22] irq6 l07 [gpio23] irq7 f06 [gpio24] irq8 h08 [gpio25] irq9 a02 [gpio26] irq10 e26 [gpio27] irq11 e24 [gpio28] irq12 c22 [gpio29] irq13 l24 [gpio30] irq14 k25 [gpio31] irq15 k22 halt n22 system 55 hisrrst ad17 iic0sclk h17 iic peripheral 54 iic0sda j16 iic1sclk h18 iic1sda h15 table 3. signals listed alph abetically (sheet 7 of 25) signal name ball interface group page
powerpc 440SPE embedded processor 24 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet irq0 [gpio16] l08 interrupts 55 irq1 [gpio17] m06 irq2 [gpio18] m08 irq3 [gpio19] e02 irq4 [gpio20] e04 irq5 [gpio21] h09 irq6 [gpio22] l07 irq7 [gpio23] f06 irq8 [gpio24] h08 irq9 [gpio25] a02 irq10 [gpio26] e26 irq11 [gpio27] e24 irq12 [gpio28] c22 irq13 [gpio29] l24 irq14 [gpio30] k25 irq15 [gpio31] k22 memaddr00 af22 ddr sdram 52 memaddr01 af19 memaddr02 ad22 memaddr03 t24 memaddr04 af18 memaddr05 ab24 memaddr06 af21 memaddr07 ae18 memaddr08 r25 memaddr09 ae20 memaddr10 ad19 memaddr11 ab26 memaddr12 r23 memaddr13 ab17 memaddr14 ae19 table 3. signals listed alph abetically (sheet 8 of 25) signal name ball interface group page
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 25 preliminary data sheet memclkout0 aa21 ddr sdram 52 memclkout0 aa20 memclkout1 ab21 memclkout1 ac21 memclkout2 ab19 memclkout2 ac19 memclkout3 aa19 memclkout3 ab20 memclkout4 aa18 memclkout4 ab18 memclkout5 ac18 memclkout5 ad18 memdata00 ac25 memdata01 aa26 memdata02 ac24 memdata03 aa25 memdata04 ad24 memdata05 ad23 memdata06 ab25 memdata07 ab23 memdata08 u19 memdata09 t21 memdata10 v19 memdata11 t20 memdata12 v21 memdata13 v22 memdata14 t18 memdata15 w22 memdata16 u24 memdata17 w25 memdata18 v23 memdata19 v24 table 3. signals listed alph abetically (sheet 9 of 25) signal name ball interface group page
powerpc 440SPE embedded processor 26 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet memdata20 y24 ddr sdram 52 memdata21 v26 memdata22 y25 memdata23 w26 memdata24 t22 memdata25 r24 memdata26 t23 memdata27 r22 memdata28 t26 memdata29 n25 memdata30 r26 memdata31 n24 memdata32 m26 memdata33 k24 memdata34 l26 memdata35 l23 memdata36 l25 memdata37 j25 memdata38 m21 memdata39 m24 memdata40 j23 memdata41 h26 memdata42 h23 memdata43 g24 memdata44 h24 memdata45 h22 memdata46 j24 memdata47 j22 memdata48 f26 table 3. signals listed alph abetically (sheet 10 of 25) signal name ball interface group page
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 27 preliminary data sheet memdata49 f23 ddr sdram 52 memdata50 f25 memdata51 e23 memdata52 e25 memdata53 d25 memdata54 d22 memdata55 d24 memdata56 c24 memdata57 c26 memdata58 b24 memdata59 a24 memdata60 b26 memdata61 b23 memdata62 a25 memdata63 b22 memdcfdbkd ae24 memdcfdbkr af24 memodt0 w21 memodt1 y22 memodt2 w20 memodt3 w19 memvref0 w18 memvref1 v16 no ball a01 table 3. signals listed alpha betically (sheet 11 of 25) signal name ball interface group page
powerpc 440SPE embedded processor 28 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet ov dd a07 power 56 ov dd a13 ov dd a14 ov dd a20 ov dd a26 ov dd g01 ov dd g07 ov dd g13 ov dd g14 ov dd g20 ov dd g26 ov dd k11 ov dd k13 ov dd k14 ov dd k16 ov dd l10 ov dd l17 ov dd m13 ov dd m14 ov dd n01 ov dd n07 ov dd n10 ov dd n12 ov dd n15 ov dd n17 ov dd n20 ov dd n26 table 3. signals listed alph abetically (sheet 12 of 25) signal name ball interface group page
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 29 preliminary data sheet pcie_pllgnda p02 power 56 pcie_pllgndb n02 pcie_pllvdd2 p09 pcie_pllvdda p03 pcie_pllvddb n03 pcie_refclk p05 pci-express 0:2 50 pcie_refclk p06 pcie0_rx0 v11 pcie0_rx0 w11 pcie0_rx1 ab11 pcie0_rx1 ac11 pcie0_rx2 w12 pcie0_rx2 y12 pcie0_rx3 ad12 pcie0_rx3 ad13 pcie0_rx4 af15 pcie0_rx4 af16 pcie0_rx5 ae16 pcie0_rx5 ad15 pcie0_rx6 v14 pcie0_rx6 w14 pcie0_rx7 w15 pcie0_rx7 w16 pcie0_tx0 y11 pcie0_tx0 aa11 pcie0_tx1 af11 pcie0_tx1 ae11 pcie0_tx2 ab12 pcie0_tx2 aa12 pcie0_tx3 ae13 pcie0_tx3 af12 table 3. signals listed alph abetically (sheet 13 of 25) signal name ball interface group page
powerpc 440SPE embedded processor 30 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet pcie0_tx4 ae14 pci-express 0:2 50 pcie0_tx4 ad14 pcie0_tx5 ab16 pcie0_tx5 ac16 pcie0_tx6 y15 pcie0_tx6 aa15 pcie0_tx7 y16 pcie0_tx7 aa16 pcie0av25 v13 pcie0avreg w13 pcie1_rx0 e20 pcie1_rx0 e21 pcie1_rx1 b21 pcie1_rx1 c20 pcie1_rx2 c19 pcie1_rx2 d19 pcie1_rx3 a19 pcie1_rx3 b19 pcie1_tx0 c21 pcie1_tx0 d21 pcie1_tx1 a21 pcie1_tx1 b20 pcie1_tx2 c18 pcie1_tx2 d18 pcie1_tx3 a18 pcie1_tx3 b18 pcie1av25 e19 pcie1avreg e18 table 3. signals listed alph abetically (sheet 14 of 25) signal name ball interface group page
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 31 preliminary data sheet pcie2_rx0 j21 pci-express 0:2 50 pcie2_rx0 k21 pcie2_rx1 j19 pcie2_rx1 k19 pcie2_rx2 f20 pcie2_rx2 f21 pcie2_rx3 f18 pcie2_rx3 f19 pcie2_tx0 l21 pcie2_tx0 l20 pcie2_tx1 j20 pcie2_tx1 h20 pcie2_tx2 g21 pcie2_tx2 h21 pcie2_tx3 g19 pcie2_tx3 h19 pcie2av25 l18 pcie2avreg l19 pciecalrn t08 pciecalrp r08 pcieplltston j01 table 3. signals listed alph abetically (sheet 15 of 25) signal name ball interface group page
powerpc 440SPE embedded processor 32 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet pcix0ack64 ad02 pci-x0 50 pcix0ad0 ab04 pcix0ad1 aa05 pcix0ad10 ab02 pcix0ad11 aa03 pcix0ad12 w05 pcix0ad13 v06 pcix0ad14 aa02 pcix0ad15 aa01 pcix0ad16 w03 pcix0ad17 w04 pcix0ad18 v05 pcix0ad19 v04 pcix0ad2 y06 pcix0ad20 v03 pcix0ad21 v02 pcix0ad22 v01 pcix0ad23 u06 pcix0ad24 t07 pcix0ad25 t06 pcix0ad26 t05 pcix0ad27 t04 pcix0ad28 t02 pcix0ad29 t01 pcix0ad3 v08 pcix0ad30 r07 pcix0ad31 r06 pcix0ad32 ad10 table 3. signals listed alph abetically (sheet 16 of 25) signal name ball interface group page
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 33 preliminary data sheet pcix0ad33 aa10 pci-x0 50 pcix0ad34 w10 pcix0ad35 af09 pcix0ad36 af08 pcix0ad37 ad09 pcix0ad38 af06 pcix0ad39 ad08 pcix0ad4 w07 pcix0ad40 ac09 pcix0ad41 ae06 pcix0ad42 ad07 pcix0ad43 ac08 pcix0ad44 ab09 pcix0ad45 ae05 pcix0ad46 ad06 pcix0ad47 ab08 pcix0ad48 aa09 pcix0ad49 y09 pcix0ad5 ac02 pcix0ad50 af03 pcix0ad51 ae04 pcix0ad52 aa08 pcix0ad53 w08 pcix0ad54 ab07 pcix0ad55 af02 pcix0ad56 ae03 pcix0ad57 ad04 pcix0ad58 ac05 pcix0ad59 ae07 pcix0ad6 aa04 pcix0ad60 w09 table 3. signals listed alph abetically (sheet 17 of 25) signal name ball interface group page
powerpc 440SPE embedded processor 34 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet pcix0ad61 u08 pci-x0 50 pcix0ad62 aa07 pcix0ad63 ae02 pcix0ad7 y05 pcix0ad8 w06 pcix0ad9 v07 pcix0be0 y03 pcix0be1 y02 pcix0be2 w02 pcix0be3 u03 pcix0be4 ab05 pcix0be5 aa06 pcix0be6 ac06 pcix0be7 ab06 pcix0calg0 ae09 pcix0calr0 ae08 pcix0cap m03 pcix0clk n05 pcix0devsel n08 pcix0ecc2 r05 pcix0ecc3 r03 pcix0ecc4 r01 pcix0ecc5 p08 pcix0frame n06 pcix0gnt0 t03 pcix0gnt1 e10 pcix0gnt2 m04 pcix0gnt3 r04 pcix0idsel u05 table 3. signals listed alph abetically (sheet 18 of 25) signal name ball interface group page
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 35 preliminary data sheet pcix0inta u02 pci-x0 50 pcix0irdy ab01 pcix0m66en a09 pcix0par w01 pcix0par64 ad03 pcix0perr n09 pcix0pllg ae01 pcix0pllv ad01 pcix0req0 r02 pcix0req1 k02 pcix0req2 k05 pcix0req3 m02 pcix0req64 ac03 pcix0reset l03 pcix0serr af05 pcix0stop ad05 pcix0trdy ab03 pcix0vc m01 pcix0vref0 y08 pcix0vref1 t09 peraddr0 e13 external slave peripheral (ebc) 54 peraddr1 e14 peraddr10 b16 peraddr11 e15 peraddr12 f11 peraddr13 d11 peraddr14 c10 peraddr15 b09 table 3. signals listed alph abetically (sheet 19 of 25) signal name ball interface group page
powerpc 440SPE embedded processor 36 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet peraddr16 c09 external slave peripheral (ebc) 54 peraddr17 a08 peraddr18 b07 peraddr19 e11 peraddr2 b15 peraddr20 e09 peraddr21 c08 peraddr22 a06 peraddr23 d08 peraddr24 a22 peraddr25 e17 peraddr26 b17 peraddr3 d15 peraddr4 h16 peraddr5 h14 peraddr6 j14 peraddr7 j13 peraddr8 a15 peraddr9 f14 perbe0 c07 perbe1 b04 perblast d16 perclk c17 percs0 c15 percs1 c11 percs2 g12 perdata00 g08 perdata01 h10 perdata02 b05 perdata03 h11 perdata04 c06 table 3. signals listed alph abetically (sheet 20 of 25) signal name ball interface group page
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 37 preliminary data sheet perdata05 j11 external slave peripheral (ebc) 54 perdata06 e08 perdata07 f07 perdata08 f09 perdata09 e06 perdata10 d05 perdata11 c04 perdata12 f08 perdata13 b03 perdata14 e07 perdata15 d06 pererr g15 peroe e05 perpar0 b06 perpar1 a03 perr/w f15 perready e16 perwe a16 psro1 u10 miscellaneous 57 pxvdd p01 power 56 pxvdd p07 pxvdd p10 pxvdd p12 pxvdd r13 pxvdd t10 pxvdd u11 pxvdd u13 pxvdd y01 pxvdd y07 pxvdd y13 table 3. signals listed alph abetically (sheet 21 of 25) signal name ball interface group page
powerpc 440SPE embedded processor 38 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet pxvdd af01 power 56 pxvdd af07 pxvdd af13 ras ae23 ddr sdram 52 scanout00 u25 tests 56 scanout07 u22 scanout08 p22 scanout14 ab10 scanout15 ae10 scanout16 ad11 scanout17 ac12 scanout18 ae12 scanout19 ab13 scanout20 ab14 scanout21 ae15 scanout25 m23 svdd p15 power 56 svdd p17 svdd p20 svdd p26 svdd r14 svdd t17 svdd u14 svdd u16 svdd y14 svdd y20 svdd y26 svdd af14 svdd af20 svdd af26 table 3. signals listed alph abetically (sheet 22 of 25) signal name ball interface group page
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 39 preliminary data sheet sys2pllg ad26 power 56 sys2pllv ae26 sysclk c16 syserr m25 syspartsel a11 syspllg b14 syspllv b13 sysreset l09 system 55 tck aa17 jtag 56 tdi ab15 tdo ad16 testen e12 thermalda aa13 miscellaneous 57 thermaldb aa14 tmr_clk k08 system 55 tms ac15 jtag 56 [trcclk] [gpio00] high z l01 trace note: trace can be enabled at reset by setting sdr0_sdstp1[dbg] (bit 27) to 1 in the serial bootstrap rom. 56 [trcbs0] [gpio01] high z h01 [trcbs1] [gpio02] high z f01 [trcbs2] [gpio03] high z l02 [trces0] [gpio04] high z k03 [trces1] [gpio05] high z g02 [trces2] [gpio06] high z m05 [trces3] [gpio07] high z f02 [trces4] [gpio08] high z j03 [trcts0] [gpio09] high z h04 [trcts1] [gpio10] high z j05 [trcts2] [gpio11] high z g05 [trcts3] [gpio12] high z l05 [trcts4] [gpio13] high z j04 [trcts5] [gpio14] high z k06 [trcts6] [gpio15] high z h06 trst ae17 jtag 56 table 3. signals listed alph abetically (sheet 23 of 25) signal name ball interface group page
powerpc 440SPE embedded processor 40 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet uartserclk h12 uart peripheral 55 uart0_cts b08 uart0_dcd h13 uart0_dsr c12 uart0_dtr c13 uart0_ri c14 uart0_rts g09 uart0_rx d12 uart0_tx d09 uart1_dsr/cts f10 uart1_dtr/rts g11 uart1_rx a12 uart1_tx b12 uart2_rx f13 uart2_tx f12 table 3. signals listed alph abetically (sheet 24 of 25) signal name ball interface group page
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 41 preliminary data sheet vdd d04 power 56 vdd d10 vdd d17 vdd d23 vdd j10 vdd j17 vdd k04 vdd k09 vdd k18 vdd k23 vdd l12 vdd l15 vdd m11 vdd m16 vdd r11 vdd r16 vdd t12 vdd t15 vdd u04 vdd u09 vdd u18 vdd u23 vdd v10 vdd v17 vdd ac04 vdd ac10 vdd ac17 vdd ac23 we ac22 ddr sdram 52 table 3. signals listed alph abetically (sheet 25 of 25) signal name ball interface group page
powerpc 440SPE embedded processor 42 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet signal list?ball assignment order in the following table, only the primary (d efault) signal name is shown for each pin. multiplexed pins are marked with an asterisk (*). to det ermine the other signals that share a pin, look up the primary signal name in table 3 on page 17. table 4. signals listed by ball assignment (sheet 1 of 7) ball signal name ball signal name ball signal name ball signal name a01 no ball b01 emcrxclk c01 emctxen d01 gnd a02 irq9 * b02 emcmdio c02 emctxclk d02 emctxerr a03 perpar1 b03 perdata13 c03 emctxd0 d03 emccrs a04 gnd b04 perbe1 c04 perdata11 d04 vdd a05 emctxd3 b05 perdata02 c05 emctxd5 d05 perdata10 a06 peraddr22 b06 perpar0 c06 perdata04 d06 perdata15 a07 ov dd b07 peraddr18 c07 perbe0 d07 gnd a08 peraddr17 b08 uart0_cts c08 peraddr21 d08 peraddr23 a09 pcix0m66en b09 peraddr15 c09 peraddr16 d09 uart0_tx a10 gnd b10 emctxd7 c10 peraddr14 d10 vdd a11 syspartsel b11 extreset c11 percs1 d11 peraddr13 a12 uart1_rx b12 uart1_tx c12 uart0_dsr d12 uart0_rx a13 ov dd b13 syspllv c13 uart0_dtr d13 gnd a14 ov dd b14 syspllg c14 uart0_ri d14 gnd a15 peraddr8 b15 peraddr2 c15 percs0 d15 peraddr3 a16 perwe b16 peraddr10 c16 sysclk d16 perblast a17 gnd b17 peraddr26 c17 perclk d17 vdd a18 pcie1_tx3 b18 pcie1_tx3 c18 pcie1_tx2 d18 pcie1_tx2 a19 pcie1_rx3 b19 pcie1_rx3 c19 pcie1_rx2 d19 pcie1_rx2 a20 ov dd b20 pcie1_tx1 c20 pcie1_rx1 d20 gnd a21 pcie1_tx1 b21 pcie1_rx1 c21 pcie1_tx0 d21 pcie1_tx0 a22 peraddr24 b22 memdata63 c22 gpio28_irq12 d22 memdata54 a23 gnd b23 memdata61 c23 dm7 d23 vdd a24 memdata59 b24 memdata58 c24 memdata56 d24 memdata55 a25 memdata62 b25 dqs7 c25 dqs7 d25 memdata53 a26 ov dd b26 memdata60 c26 memdata57 d26 gnd
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 43 preliminary data sheet e01 emctxd6 f01 trcbs1 * g01 ov dd h01 trcbs0 * e02 gpio19_irq3 f02 trces3 * g02 trces1 * h02 emcrxd3 e03 emctxd4 f03 emcmdclk g03 emcrxd2 h03 emcrxd4 e04 irq4 * f04 emcrxerr g04 gnd h04 trcts0 * e05 peroe f05 emcrxd7 g05 trcts2 * h05 emccd e06 perdata09 f06 irq7 * g06 emctxd1 h06 trcts6 * e07 perdata14 f07 perdata07 g07 ov dd h07 emcrefclk e08 perdata06 f08 perdata12 g08 perdata00 h08 irq8 * e09 peraddr20 f09 perdata08 g09 uart0_rts h09 irq5 * e10 pcix0gnt1 f10 uart1_dsr/cts g10 gnd h10 perdata01 e11 peraddr19 f11 peraddr12 g11 uart1_dtr/rts h11 perdata03 e12 testen f12 uart2_tx g12 percs2 h12 uartserclk e13 peraddr0 f13 uart2_rx g13 ov dd h13 uart0_dcd e14 peraddr1 f14 peraddr9 g14 ov dd h14 peraddr5 e15 peraddr11 f15 perr/w g15 pererr h15 iic1sda e16 perready f16 reserved g16 reserved h16 peraddr4 e17 peraddr25 f17 reserved g17 gnd h17 iic0sclk e18 pcie1avreg f18 pcie2_rx3 g18 reserved h18 iic1sclk e19 pcie1av25 f19 pcie2_rx3 g19 pcie2_tx3 h19 pcie2_tx3 e20 pcie1_rx0 f20 pcie2_rx2 g20 ov dd h20 pcie2_tx1 e21 pcie1_rx0 f21 pcie2_rx2 g21 pcie2_tx2 h21 pcie2_tx2 e22 dqs6 f22 dqs6 g22 dm5 h22 memdata45 e23 memdata51 f23 memdata49 g23 gnd h23 memdata42 e24 irq11 * f24 dm6 g24 memdata43 h24 memdata44 e25 memdata52 f25 memdata50 g25 dqs5 h25 dqs5 e26 irq10 * f26 memdata48 g26 ov dd h26 memdata41 table 4. signals listed by ball assignment (sheet 2 of 7) ball signal name ball signal name ball signal name ball signal name
powerpc 440SPE embedded processor 44 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet j01 pcieplltston k01 gnd l01 trcclk * m01 pcix0vc j02 emcrxd1 k02 pcix0req1 l02 trcbs2 * m02 pcix0req3 j03 trces4 * k03 trces0 * l03 pcix0reset m03 pcix0cap j04 trcts4 * k04 vdd l04 emcrxd5 m04 pcix0gnt2 j05 trcts1 * k05 pcix0req2 l05 trcts3 * m05 trces2 * j06 emcrxdv k06 trcts5 * l06 emcrxd0 m06 irq1 * j07 emctxd2 k07 gnd l07 irq6 * m07 emcrxd6 j08 emcgtxclk k08 tmr_clk l08 irq0 * m08 irq2 * j09 gnd k09 vdd l09 sysreset m09 gnd j10 vdd k10 gnd l10 ov dd m10 gnd j11 perdata05 k11 ov dd l11 gnd m11 vdd j12 gnd k12 gnd l12 vdd m12 gnd j13 peraddr7 k13 ov dd l13 gnd m13 ov dd j14 peraddr6 k14 ov dd l14 gnd m14 ov dd j15 gnd k15 gnd l15 vdd m15 gnd j16 iic0sda k16 ov dd l16 gnd m16 vdd j17 vdd k17 gnd l17 ov dd m17 gnd j18 gnd k18 vdd l18 pcie2av25 m18 gnd j19 pcie2_rx1 k19 pcie2_rx1 l19 pcie2avreg m19 dm8 j20 pcie2_tx1 k20 gnd l20 pcie2_tx0 m20 ecc2 j21 pcie2_rx0 k21 pcie2_rx0 l21 pcie2_tx0 m21 memdata38 j22 memdata47 k22 irq15 * l22 dqs4 m22 dqs4 j23 memdata40 k23 vdd l23 memdata35 m23 scanout25 j24 memdata46 k24 memdata33 l24 irq13 * m24 memdata39 j25 memdata37 k25 irq14 * l25 memdata36 m25 syserr j26 dm4 k26 gnd l26 memdata34 m26 memdata32 table 4. signals listed by ball assignment (sheet 3 of 7) ball signal name ball signal name ball signal name ball signal name
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 45 preliminary data sheet n01 ov dd p01 pxv dd r01 pcix0ecc4 t01 pcix0ad29 n02 pcie_pllgndb p02 pcie_pllgnda r02 pcix0req0 t02 pcix0ad28 n03 pcie_pllvddb p03 pcie_pllvdda r03 pcix0ecc3 t03 pcix0gnt0 n04 gnd p04 gnd r04 pcix0gnt3 t04 pcix0ad27 n05 pcix0clk p05 pcie_refclk r05 pcix0ecc2 t05 pcix0ad26 n06 pcix0frame p06 pcie_refclk r06 pcix0ad31 t06 pcix0ad25 n07 ov dd p07 pxv dd r07 pcix0ad30 t07 pcix0ad24 n08 pcix0devsel p08 pcix0ecc5 r08 pciecalrp t08 pciecalrn n09 pcix0perr p09 pcie_pllvdd2 r09 gnd t09 pcix0vref1 n10 ov dd p10 pxv dd r10 gnd t10 pxv dd n11 gnd p11 gnd r11 vdd t11 gnd n12 ov dd p12 pxv dd r12 gnd t12 vdd n13 gnd p13 gnd r13 pxv dd t13 gnd n14 gnd p14 gnd r14 sv dd t14 gnd n15 ov dd p15 sv dd r15 gnd t15 vdd n16 gnd p16 gnd r16 vdd t16 gnd n17 ov dd p17 sv dd r17 gnd t17 sv dd n18 ecc7 p18 ecc3 r18 gnd t18 memdata14 n19 ecc5 p19 ecc4 r19 ecc0 t19 dqs1 n20 ov dd p20 sv dd r20 ecc1 t20 memdata11 n21 ecc6 p21 dqs8 r21 dqs8 t21 memdata09 n22 halt p22 scanout08 r22 memdata27 t22 memdata24 n23 gnd p23 gnd r23 memaddr12 t23 memdata26 n24 memdata31 p24 dqs3 r24 memdata25 t24 memaddr03 n25 memdata29 p25 dqs3 r25 memaddr08 t25 dm3 n26 ov dd p26 sv dd r26 memdata30 t26 memdata28 table 4. signals listed by ball assignment (sheet 4 of 7) ball signal name ball signal name ball signal name ball signal name
powerpc 440SPE embedded processor 46 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet u01 gnd v01 pcix0ad22 w01 pcix0par y01 pxv dd u02 pcix0inta v02 pcix0ad21 w02 pcix0be2 y02 pcix0be1 u03 pcix0be3 v03 pcix0ad20 w03 pcix0ad16 y03 pcix0be0 u04 vdd v04 pcix0ad19 w04 pcix0ad17 y04 gnd u05 pcix0idsel v05 pcix0ad18 w05 pcix0ad12 y05 pcix0ad7 u06 pcix0ad23 v06 pcix0ad13 w06 pcix0ad8 y06 pcix0ad2 u07 gnd v07 pcix0ad9 w07 pcix0ad4 y07 pxv dd u08 pcix0ad61 v08 pcix0ad3 w08 pcix0ad53 y08 pcix0vref0 u09 vdd v09 gnd w09 pcix0ad60 y09 pcix0ad49 u10 psro1 v10 vdd w10 pcix0ad34 y10 gnd u11 pxv dd v11 pcie0_rx0 w11 pcie0_rx0 y11 pcie0_tx0 u12 gnd v12 gnd w12 pcie0_rx2 y12 pcie0_rx2 u13 pxv dd v13 pcie0av25 w13 pcie0avreg y13 pxv dd u14 sv dd v14 pcie0_rx6 w14 pcie0_rx6 y14 sv dd u15 gnd v15 gnd w15 pcie0_rx7 y15 pcie0_tx6 u16 sv dd v16 memvref1 w16 pcie0_rx7 y16 pcie0_tx7 u17 gnd v17 vdd w17 banksel3 y17 gnd u18 vdd v18 gnd w18 memvref0 y18 banksel1 u19 memdata08 v19 memdata10 w19 memodt3 y19 banksel2 u20 gnd v20 dm1 w20 memodt2 y20 sv dd u21 dqs1 v21 memdata12 w21 memodt0 y21 clken0 u22 scanout07 v22 memdata13 w22 memdata15 y22 memodt1 u23 vdd v23 memdata18 w23 dqs2 y23 gnd u24 memdata16 v24 memdata19 w24 dqs2 y24 memdata20 u25 scanout00 v25 dm2 w25 memdata17 y25 memdata22 u26 gnd v26 memdata21 w26 memdata23 y26 sv dd table 4. signals listed by ball assignment (sheet 5 of 7) ball signal name ball signal name ball signal name ball signal name
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 47 preliminary data sheet aa01 pcix0ad15 ab01 pcix0irdy ac01 gnd ad01 pcix0pllv aa02 pcix0ad14 ab02 pcix0ad10 ac02 pcix0ad5 ad02 pcix0ack64 aa03 pcix0ad11 ab03 pcix0trdy ac03 pcix0req64 ad03 pcix0par64 aa04 pcix0ad6 ab04 pcix0ad0 ac04 vdd ad04 pcix0ad57 aa05 pcix0ad1 ab05 pcix0be4 ac05 pcix0ad58 ad05 pcix0stop aa06 pcix0be5 ab06 pcix0be7 ac06 pcix0be6 ad06 pcix0ad46 aa07 pcix0ad62 ab07 pcix0ad54 ac07 gnd ad07 pcix0ad42 aa08 pcix0ad52 ab08 pcix0ad47 ac08 pcix0ad43 ad08 pcix0ad39 aa09 pcix0ad48 ab09 pcix0ad44 ac09 pcix0ad40 ad09 pcix0ad37 aa10 pcix0ad33 ab10 scanout14 ac10 vdd ad10 pcix0ad32 aa11 pcie0_tx0 ab11 pcie0_rx1 ac11 pcie0_rx1 ad11 scanout16 aa12 pcie0_tx2 ab12 pcie0_tx2 ac12 scanout17 ad12 pcie0_rx3 aa13 thermalda ab13 scanout19 ac13 gnd ad13 pcie0_rx3 aa14 thermaldb ab14 scanout20 ac14 gnd ad14 pcie0_tx4 aa15 pcie0_tx6 ab15 tdi ac15 tms ad15 pcie0_rx5 aa16 pcie0_tx7 ab16 pcie0_tx5 ac16 pcie0_tx5 ad16 tdo aa17 tck ab17 memaddr13 ac17 vdd ad17 hisrrst aa18 memclkout4 ab18 memclkout4 ac18 memclkout5 ad18 memclkout5 aa19 memclkout3 ab19 memclkout2 ac19 memclkout2 ad19 memaddr10 aa20 memclkout0 ab20 memclkout3 ac20 gnd ad20 banksel0 aa21 memclkout0 ab21 memclkout1 ac21 memclkout1 ad21 ba1 aa22 clken1 ab22 cas ac22 we ad22 memaddr02 aa23 dqs0 ab23 memdata07 ac23 vdd ad23 memdata05 aa24 dqs0 ab24 memaddr05 ac24 memdata02 ad24 memdata04 aa25 memdata03 ab25 memdata06 ac25 memdata00 ad25 dm0 aa26 memdata01 ab26 memaddr11 ac26 gnd ad26 sys2pllg table 4. signals listed by ball assignment (sheet 6 of 7) ball signal name ball signal name ball signal name ball signal name
powerpc 440SPE embedded processor 48 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet ae01 pcix0pllg af01 pxv dd ae02 pcix0ad63 af02 pcix0ad55 ae03 pcix0ad56 af03 pcix0ad50 ae04 pcix0ad51 af04 gnd ae05 pcix0ad45 af05 pcix0serr ae06 pcix0ad41 af06 pcix0ad38 ae07 pcix0ad59 af07 pxv dd ae08 pcix0calr0 af08 pcix0ad36 ae09 pcix0calg0 af09 pcix0ad35 ae10 scanout15 af10 gnd ae11 pcie0_tx1 af11 pcie0_tx1 ae12 scanout18 af12 pcie0_tx3 ae13 pcie0_tx3 af13 pxv dd ae14 pcie0_tx4 af14 sv dd ae15 scanout21 af15 pcie0_rx4 ae16 pcie0_rx5 af16 pcie0_rx4 ae17 trst af17 gnd ae18 memaddr07 af18 memaddr04 ae19 memaddr14 af19 memaddr01 ae20 memaddr09 af20 sv dd ae21 ba2 af21 memaddr06 ae22 ba0 af22 memaddr00 ae23 ras af23 gnd ae24 memdcfdbkd af24 memdcfdbkr ae25 clken2 af25 clken3 ae26 sys2pllv af26 sv dd table 4. signals listed by ball assignment (sheet 7 of 7) ball signal name ball signal name ball signal name ball signal name
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 49 preliminary data sheet signal description the ppc440SPE embedded controller is packaged in a 27mm flip-chip plastic ball grid array (fc-pbga). the following tables describe the package level pinout. in the table ?signal functional description? on page 50, each i/o signal is listed along with a short description of its function. active-low signals (for example, ras ) are marked with an overline. see ?signals listed alphabetically? on page 17 for the pin (ball) number to which each signal is assigned. multiplexed signals some signals are multiplexed on the same pin so that the pin can be used for different functions. the signal names shown in table 6 on page 50 are not accompanied by signal nam es that might be multiplexed on the same pin. it is expected that in any single applicat ion a particular pin will always be progra mmed to serve the sa me function. the flexibility of multiplexing allows a si ngle chip to offer a ri cher pin selection than wo uld otherwise be possible. strapping pins one group of pins is used as strapped inputs during syst em reset. these pins function as strapped inputs only during reset and are used for other functions during no rmal operation (see ?strapping? on page 77). note that these are not multiplexed pins since the function of the pins is not programmable. multipurpose signals in addition to multiplexing, some pins are also multi- purpose. for example, the pcix 0ack can function instead as pcix0ecc1 depending on the pci interface mode of operation. table 5. pin summary group no. of pins total signal pins 495 axv dd (1.5v) 3 axv dd (2.5v hss) 6 axgnd 5 ov dd (3.3v i/os) 23 pxv dd (3.3/1.5v pci) 14 sv dd (2.5/1.8v sdram) 14 v dd (1.5v logic) 28 gnd 83 total power pins reserved 4 total pins 675
powerpc 440SPE embedded processor 50 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet table 6. signal functional description (sheet 1 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v ) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes pci-express 0:2 interfaces pcie_refclk pcie_refclk pci express reference clock: 100 mhz differential clock pair. input type is c ontrolled by bit 3 of the pesdr0_plllct1[mcent] register. 0 2.5v cmos or lvds 1 2.5v lvpecl (recommended) i diff pecl pcie0tx[7:0] pcie0tx[7:0] pcie1:2tx[3:0] pcie1:2tx[3:0] pci express serial data transmit differential signals lsb is 0. x8 mode: all pcie0tx[7:0] /pcie0tx[7:0] are used. x4 mode: only pcie0tx[3:0] /pcie0tx[3:0] are used. o diff pecl pcie0rx[7:0] pcie0rx[7:0] pcie1:2rx[3:0] pcie1:2rx[3:0] pci express serial data receive differential signals lsb is 0. x8 mode: all pcie0rx[7:0] /pcie0rx[7:0] are used. x4 mode: only pcie0rx[3:0] /pcie0rx[3:0] are used i diff pecl pcie0:2avreg pci express analog observation point for internal voltage regulator o pciecalrp pciecalrn positive and negative inputs for a 1 kohm 1% pci express external calibration resistor i pcieplltston enable pci express pll test modes. i pci-x0 interfaces pcix0ack64 /pcix0ecc1 ack64 or ecc1. normally used as ack64 indicating that the target can transfer data using 64 bits. or used as ecc1 for pcix mode 2. i/o 3.3v pci or 1.5v pci for mode 2 4 pcix0ad63:00 address/data bus (bidirectional) for pci-x0 i/o 3.3v pci or 1.5v pci for mode 2 pcix0be7:0 pci-x byte enables for pci-x0 i/o 3.3v pci or 1.5v pci for mode 2 pcix0calg0 pcix0calr0 balls g and r for a 114 ohm external calibration resistor. used to control pci-x i/o impedance at 57 ohm. ina pcix0cap capable of pci-x operation. this analog input is sampled to configure pci and determine the state of the pcix0vc output signal: 0.00v dd (0.0v) = conventional pci & pcix0vc = 0 0.49v dd (1.0v) = pci-x ddr 266 mode 2 & pcix0vc = 1 0.75v dd (2.5v) = pci-x 66 & pcix0vc = 0 1.00v dd (3.3v) = pci-x 133 & pcix0vc = 0 ina
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 51 preliminary data sheet pcix0clk input pci & pci-x clock. note: if the pci-x interface is not being used, drive this pin with a 3.3v clock signal at a frequency between 1 and 66mhz i 3.3v pci pcix0devsel indicates the driving device has decoded its address as the target of the current access. i/o 3.3v pci 4 pcix0ecc5:2 ecc check bits 5?2. all ecc bi ts are valid only for pcix ddr mode 2. note: see pcixpar for ecc0. see pcixack64 for ecc1. see pcixreq64 for ecc6. see pcixpar64 for ecc7. i/o 3.3v pci or 1.5v pci for mode 2 pcix0frame driven by the current master to indicate beginning and duration of an access. i/o 3.3v pci 4 pcix0gnt0 pcix0gnt1:3 indicates that the specified agent is granted access to the pci-x bus. when arbitration is internal to the ppc440SPE, all grants gnt0:3 are outputs. when arbitration is external, onl y gnt 0 is used as an input. i/o o 3.3v pci 4 pcix0idsel used as a chip select during configuration read and write transactions. if the pci-x is a host, during configuration the isdsel is an output that duplicates the ad17. the isdsel is always 3.3v even in mode 2 ddr i/o 3.3v pci 5 pcix0inta level sensitive pci interrupt. o 3.3v pci pcix0irdy indicates initiating agent?s ability to complete the current data phase of the transaction. i/o 3.3v pci 4 pcix0m66en capable of 66mhz operation. i 3.3v pci or 1.5v pci for mode 2 pcix0par/pcix0ecc0 even parity indicator or ecc0. normally used to indica te even parity across pciad31:00 and be3:0. used as ecc0 for pcix0 mode 2. i/o 3.3v pci or 1.5v pci for mode 2 pcix0par64/pcix0ecc7 even parity indicator or ecc7. normally used to indica te even parity across pcixad63:32 and be7:4 for pcix0 or used as ecc7 for pcix0 mode 2. i/o 3.3v pci or 1.5v pci for mode 2 pcix0perr reports data parity errors during all pci transactions except a special cycle. i/o 3.3v pci 4 pcix0req0 pcix0req1:3 an indication to the pci-x arbiter that the specified agent wishes to use the bus. when arbitration is internal to the ppc440SPE, all reqs req0:3 are inputs. when arbitration is external, only req 0 is used as an output. i/o i 3.3v pci 4 table 6. signal functional description (sheet 2 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v ) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
powerpc 440SPE embedded processor 52 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet pcix0req64/pcix0ecc6 request 64-bit transfer or ecc6. normally used by the current bus master to indicate a 64-bit transfer. used as ecc6 for pcix0 mode 2. i/o 3.3v pci or 1.5v pci for mode 2 4 pcix0reset sets pci device registers and logic to a consistent state. o 3.3v pci pcix0serr reports address parity errors, data parity errors on the special cycle command, or other catastrophic system errors. i/o 3.3v pci 4 pcix0stop indicates the current target is requesting the master to stop the current transaction. i/o 3.3v pci 4 pcix0trdy i ndicates the target agent?s ability to complete the current data phase of the transaction. i/o 3.3v pci 4 pcix0vc voltage control output. used to control the voltage regulator supplying the pci i/o voltage. see pcix0cap signal. 0 = 3.3v (pci i/o) 1 =1.5v (pci-x ddr) o 3.3(1.5)v pci pcix0vref0:1 voltage reference input for pci-x mode 2/ddr (1.5v) i/o. not used for pci or pci-x mode 1. i vpcixddr 5 ddr sdram interface ba0:2 bank address supporting up to 8 internal banks. o 2.5(1.8)v ddr sdram banksel0:3 selects up to four external ddr sdram banks. o 2.5(1.8)v ddr sdram cas column address strobe. o 2.5(1.8)v ddr sdram clken0:3 clock enable. one for each external bank. o 2.5(1.8)v ddr sdram dm0:8 memory write data byte lane masks. memdm8 is the byte lane mask for the ecc byte lane. o 2.5(1.8)v ddr sdram dqs0:8 dqs0:8 byte lane data strobe. dqs8 is the data strobe for the ecc byte lane. these signals are differential pairs. i/o 2.5(1.8)v ddr sdram diff ecc0:7 ecc check bits 0:7. i/o 2.5(1.8)v ddr sdram memaddr14:00 memory address bus. note: memaddr14 is the most significant bit (msb). o 2.5(1.8)v ddr sdram memclkout0:5 memclkout0:5 subsystem clocks. the clock si gnal (differential pair) is duplicated six times to support high loading: six clocks can be used for two unbuffered dimms. each individual clock signal can be enabled by programming the sdr0_ddrclkset register. o 2.5(1.8)v ddr sdram diff memdata63:00 memory data bus. note: memdata63 is the most significant bit (msb). i/o 2.5(1.8)v ddr sdram table 6. signal functional description (sheet 3 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v ) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 53 preliminary data sheet memdcfdbkd feedback driver, for i/o timing measurements. o 2.5(1.8)v ddr sdram memdcfdbkr feedback receiver. connect externally to memdcfdbkd. i 2.5(1.8)v ddr sdram memodt0:3 memory on-die termination control o 2.5(1.8)v ddr sdram memvref0 memory reference voltage (sv ref ) input. i 2.5(1.8)v ddr sdram volt ref rcv memvref1 memory reference voltage (sv ref ) supplemental input. i 2.5(1.8)v ddr sdram volt ref sup ras row address strobe. o 2.5(1.8)v ddr sdram we write enable. o 2.5(1.8)v ddr sdram ethernet interface emccd collision detection. i 3.3v lvttl emccrs carrier sense. i 3.3v lvttl emcmdclk management data clock. o 3.3v lvttl emcmdio transfer command and status information between mii and phy. i/o 3.3v lvttl emcrxd0:7 receive data. i 3.3v lvttl emcrxdv receive data valid. i 3.3v lvttl emcrxerr receive error. i 3.3v lvttl emcrxclk receive clock. i 3.3v lvttl emcrefclk reference clock.typical use: gmii gigabit interface i 3.3v lvttl emctxclk transmit clock for 10/100 mb/s. i 3.3v lvttl emcgtxclk ethernet gigabit transmit clock. 125mhz to phy o 3.3v lvttl emctxd0:7 transmit data. o 3.3v lvttl emctxen transmit data enabled. o 3.3v lvttl emctxerr transmit error. o 3.3v lvttl table 6. signal functional description (sheet 4 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v ) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
powerpc 440SPE embedded processor 54 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet external slave peripheral interface - ebc peraddr00:26 peripheral address bus. note: peraddr00 is the most significant bit (msb). o3.3v lvttl 1 perbe0:1 external peripheral data bus byte enable. o 3.3v lvttl 1 perblast used by the peripheral controller to indicates the last transfer of a memory access. o3.3v lvttl percs0:2 external peripheral device select. o 3.3v lvttl perdata00:15 peripheral data bus. note: perdata0 is the most significant bit (msb). i/o 3.3v lvttl 1 peroe used by peripheral contro ller or dma controller depending upon the type of transfer involved. when the ppc440SPE is the bus master, it enables the selected device to drive the bus. o3.3v lvttl perpar0:1 external peripheral data bus byte parity. i/o 3.3v lvttl 1 perready used by a peripheral slave to indicate it is ready to transfer data. i3.3v lvttl perr/w the peripheral controller set this signal to high for a read from external memory, and to low for a write. o3.3v lvttl 1 perwe write enable. o 3.3v lvttl perclk peripheral clock used by synchrono us peripheral slaves. o 3.3v lvttl pererr external error used as an input to record external slave peripheral errors. i 3.3v lvttl 1, 5 iic peripheral interface iic0sclk iic0 serial clock. i/o 3.3v iic 1, 2 iic0sda iic0 serial data. i/o 3.3v iic 1, 2 iic1sclk iic1 serial clock. i/o 3.3v iic 1, 2 iic1sda iic1 serial data. i/o 3.3v iic 1, 2 table 6. signal functional description (sheet 5 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v ) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 55 preliminary data sheet uart peripheral interface uartserclk serial clock input that prov ides an alternative to the internally generated serial cl ock. used in cases where the allowable internally generated clock rates are not satisfactory. i 3.3v lvttl 1, 4 uart0_rx uart0 receive data. i 3.3v lvttl 1, 4 uart0_tx uart0 transmit data. o 3.3v lvttl 4 uart0_dcd uart0 data carrier detect. i 3.3v lvttl 6 uart0_dsr uart0 data set ready. i 3.3v lvttl 6 uart0_cts uart0 clear to send. i 3.3v lvttl 1, 4, 6 uart0_dtr uart0 data terminal ready. o 3.3v lvttl 4 uart0_rts uart0 request to send. o 3.3v lvttl 4 uart0_ri uart0 ring indicator. i 3.3v lvttl w/pull-up 1, 4 uart1_rx uart1 receive data. i 3.3v lvttl 1, 4 uart1_tx uart1 transmit data. o 3.3v lvttl 1, 4 uart1_dsr /cts uart1 data set ready or clear to send. the choice is determined by a dcr register bit setting. i 3.3v lvttl 1, 4 uart1_dtr/rts uart1 request to send or data terminal ready. the choice is determined by a dcr register bit setting. o 3.3v lvttl 1, 4 uart2_rx uart2 receive data. i 3.3v lvttl 1, 4 uart2_tx uart2 transmit data. o 3.3v lvttl 1, 4 interrupts interface irq0:15 external interrupt requests 0 through 15. these pins are multiplexed with gpio16:31 i 3.3v lvttl 1, 5 system interface halt halt from external debugger. i 3.3v lvttl 1, 4 gpio00:31 general purpose i/o 0 through 31. the gpios are multiplexed with irqs, and trace signal io. setting is done with the dcr register bits. i/o 3.3v lvttl sysclk main system clock input. i 3.3v lvttl syserr set to 1 when a machine check is generated. o 3.3v lvttl syspartsel not used. i na 3 sysreset main system reset. external logic can drive this pin low (minimum of 16 cycles) to initiate a system reset. a reset of the ppc440SPE can also be initiated by software. i 3.3v lvttl 1, 2 extreset external reset. during the ppc440SPE?s reset phase this signal is at down level. o3.3v lvttl table 6. signal functional description (sheet 6 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v ) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
powerpc 440SPE embedded processor 56 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet hisrrst hardware initiated system reset with an initial sdram self-refresh phase to save data in memory. i 3.3v lvttl 1, 2 testen test enable. i 3.3v lvttl 3 tmr_clk processor timer exter nal input clock. i 3.3v lvttl jtag interface tck test clock. i 3.3v lvttl 1 tdi test data in. i 3.3v lvttl w/pull-down 4 tdo test data out. o 3.3v lvttl tms test mode select. i 3.3v lvttl with pull-up 1 trst test reset. during chip power-up, this signal must be low from the start of vdd ramp-up until at least 16 sysclk cycles after vdd is stabl e in order to initialize the jtag controller. i 3.3v lvttl with pull-up 5 trace interface trcclk trace data capture clock, runs at 1/4 the frequency of the processor. o3.3v lvttl trcbs0:2 trace branch execution status. o 3.3v lvttl trces0:4 trace execution status is presented every fourth processor clock cycle. o3.3v lvttl trcts0:6 additional information on tr ace execution and branch status. o3.3v lvttl tests scanout[00][07:08] [14:21] [25] test scan out manufacturing test signals: no need for termination n/a power pcie0:2av25 2.5v supply voltage for the serial link of the pci express i pcie_pllvdd2 2.5v supply voltage for the pci express reference clock input receiver in front of the pll i pcie_pllvdda analog 2.5v filtered supply voltage a for the pll of the pci express i pcie_pllvddb analog 2.5v filtered supply voltage b for the pll of the pci express i pcie_pllgnda gnda for the pll of the pci express i pcie_pllgndb gndb for the pll of the pci express i pcix0pllg ground for the pci-x0 pll n/a n/a pcix0pllv analog 1.5v filtered supply voltages input for pci-x0 a separate filter for all analog voltages is recommended. in/a table 6. signal functional description (sheet 7 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v ) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 57 preliminary data sheet syspllg ground for the sys_pll n/a n/a syspllv analog 1.5v filtered supply voltages input for the sys_pll a separate filter for all analog voltages is recommended. in/a sys2pllg ground for the ddr_pll (sdram) n/a n/a sys2pllv analog 1.5v filtered supply voltages input for the ddr_pll (sdram) a separate filter for all analog voltages is recommended. in/a gnd logic and i/o voltage ground. n/a n/a ov dd 3.3v i/o supply (except ddr sdram and pci-x). n/a n/a pxv dd pci-x i/o voltage supply. 3.3 v for pci and pci-x 1.5 v for pci-x 266 ddr mode 2 n/a n/a sv dd ddr sdram i/o voltage supply. 2.5v for ddr1 sdram 1.8v for ddr2 sdram n/a n/a v dd 1.5v logic voltage supply. n/a n/a miscellaneous psro1 performance screen ring oscillator. n/a n/a 5 thermalda thermaldb on chip diode for thermal monitoring. p diffusion on pad a (in), and n on pad b (out) i o reserved do not connect voltage, ground, or any signals to these pins. n/a n/a table 6. signal functional description (sheet 8 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v ) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
powerpc 440SPE embedded processor 58 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet device characteristics table 7. absolute maximum ratings the absolute maximum ratings bel ow are stress ratings only. operation at or beyond these maximum ratings can cause permanent damage to the device. none of the performance spec ification contained in this document are guaranteed when operating at these maximum ratings. characteristic symbol value unit notes supply voltage (internal logic) v dd 0 to +1.6 v supply voltage (i/o interface, except ddr sdram) ov dd 0 to +3.6 v supply voltage (pci-x i/o) pxv dd 0 to +3.6 v supply voltage (pci-x ddr i/o) pxv dd 0 to +1.6 v supply voltages (system plls) axv dd 0 to +1.6 v 1 supply voltages (pci-x plls) apxv dd 0 to +1.6 v 1 supply voltage (ddr sdram logic) sv dd 0 to +2.7 v supply voltage (ddr2 sdram logic) sv dd 0 to +1.95 v input voltage (3.3v lvttl receivers) v in 0 to +3.6 v storage temperature range t stg -55 to +150 c case temperature under bias t c -40 to +120 c2 notes: 1. the analog voltages used for the on-chip p lls can be derived from the logic voltage, but must be filtered before entering the ppc440SPE. a separate filter, as shown below, is recommended for each voltage: 2. this value is not a specificatio n of the operational temperature range, it is a stress rating only. v dd c axv dd , apxv dd l l ? smt ferrite bead chip, murata blm31a700s c ? 0.1 f ceramic murata blm15ag102sn1 c ? 1 f ceramic pcie_pllvdda & b pci express
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 59 preliminary data sheet table 8. package thermal specifications thermal resistance values for the ppc440SPE package in a convection environment are as follows: parameter symbol airflow ft/min (m/sec) unit notes 0 (0) 100 (0.51) 200 (1.02) junction-to-case thermal resistance jc 0.8 0.8 0.8 c/w 1 case-to-ambient thermal resistance (w/o heat sink) ca 15.5 13.1 11.9 c/w 2 range minimum maximum junction-to-ball (typical) jb 6.5 6.5 c/w 3 notes: 1. case temperature, t c , is measured at top center of case surface with devic e soldered to circuit board. for this part the junction temperature and the case temperature are essentially identical. 2. the case-to-ambient thermal resistance is measured in a jedec jesd51-6 standard environment; and may not accurately predict thermal performance in production equipment environments. the operational case temperature must be maintained. 3. 6.5 c/w is the theoretical jb using an infinite heat sink. the larger number applies to the module mounted on a 1.8mm thick, 2p card using 1oz. copper power planes, with an effective heat transfer area of 75mm 2 . table 9. recommended dc operat ing conditions (sheet 1 of 3) device operation beyond the conditions specified is not recommended. extended ope ration beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes logic supply voltage v dd +1.425 +1.5 +1.575 v 4 i/o supply voltage ov dd +3.0 +3.3 +3.6 v 4 pci & pci-x i/o supply voltage pci-x ddr mode 2 pxv dd +3.0 +1.425 +3.3 +1.5 +3.6 +1.575 v4 voltage reference input for pci-x ddr mode 2 pcix0vref0:1 +1.425 +1.5 +1.575 v 4 ddr1 sdram supply voltage (ddr400) ddr2 sdram sv dd +2.3 +1.7 +2.5 (2.6) +1.8 +2.7 +1.9 v4 analog system and ddr pll supply voltages axv dd +1.4 +1.5 +1.6 v 3 analog pci express pll supply voltage apexv dd + 1.65 +2.5 +2.75 v analog pci-x pll supply voltages apxv dd +1.4 +1.5 +1.6 v 3 ddr1 sdram reference voltage sv ref +1.15 +1.25 +1.35 v 3 ddr2 sdram reference voltage sv ref 0.49 x sv dd 0.50 x sv dd 0.51 x sv dd v
powerpc 440SPE embedded processor 60 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet input logic high (2.5v ddr sdram) v ih sv ref +0.18 sv dd +0.3 v2 input logic high (1.8v ddr2 sdram) sv ref +0.125 sv dd +0.3 v input logic high (2.5v cmos, 3.3v tolerant receiver) 1.7 v input logic high (3.3v pci-x) 0.5ov dd ov dd +0.5 v1 input logic high (1.5v pci-x ddr) - - v 1 input logic high (3.3v lvttl) +2.0 +3.6 v input logic low (2.5v ddr sdram) v il -0.3 sv ref -0.18 v input logic low (1.8v ddr2 sdram) -0.3 sv ref -0.125 v input logic low (2.5v cmos, 3.3v tolerant receiver) 0.7 v input logic low (3.3v pci-x) -0.5 0.35ov dd v1 input logic low (1.5v pci-x ddr) - - v 1 input logic low (3.3v lvttl) 0 +0.8 v output logic high (2.5v ddr sdram) v oh +1.95 sv dd v output logic high (1.8v ddr2 sdram) sv dd -0.45 sv dd v output logic high (2.5v cmos, 3.3v tolerant receiver) 2.0 v output logic high (3.3v pci-x) 0.9ov dd ov dd v1 output logic high (1.5v pci-x ddr) - - v 1 output logic high (3.3v lvttl) +2.4 ov dd v output logic low (2.5v ddr sdram) v ol 00.45v output logic low (1.8v ddr2 sdram) 0 0.45 v output logic low (2.5v cmos, 3.3v tolerant receiver) 0.4 v output logic low (3.3v pci-x) 0.1ov dd v1 output logic low (1.5v pci-x ddr) - - v 1 output logic low (3.3v lvttl) 0 +0.4 v input leakage current (with no internal pull-up or pull-down) i il1 01 a input leakage current (with internal pull-down) i il2 0 (lpdl) 200 (mpul) a5 input leakage current (with internal pull-up) i il3 -150 (lpdl) 0 (mpul) a5 table 9. recommended dc operat ing conditions (sheet 2 of 3) device operation beyond the conditions specified is not recommended. extended ope ration beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 61 preliminary data sheet input max allowable overshoot (3.3v lvttl) v imao +3.9 v input max allowable undershoot (3.3v lvttl) v imau -0.6 v output max allowable overshoot (3.3v lvttl) v omao +3.9 v output max allowable undershoot (3.3v lvttl) v omau3 -0.6 v case temperature t c 0+95 c6 notes: 1. pci-x drivers meet pci-x specifications. 2. sv ref = sv dd /2 3. the analog voltages used for the on-chip plls can be derived fr om the logic voltage, but must be filtered before entering the ppc440SPE. see ?absolute maximum ratings? on page 58. 4. during chip power-up, ov dd should begin to ramp before vdd. external volta ge should not be applied to the chip i/o pins before ov dd is applied to the chip. a power-down cycle should complete (ov dd and vdd should both be below 0.4v) before a new power up cycle is started. 5. lpdl is least positive down level; mpul is most positive up level. 6. case temperature, t c , is measured at top center of case su rface with device soldered to circuit board. table 10. input capacitance parameter symbol maximum unit notes group 1 (2.5v sstl i/o) c in1 5.7 pf group 2 (3.3v lvttl i/o) c in2 6.8 pf group 3 (pci-x i/o) c in3 5.1 pf group 4 (receivers) c in4 6.7 pf group 5 (3.3v tolerant cmos i/o) c in5 2.6 pf table 9. recommended dc operat ing conditions (sheet 3 of 3) device operation beyond the conditions specified is not recommended. extended ope ration beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes
powerpc 440SPE embedded processor 62 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet clock test conditions clock timing and switching characteristics ar e specified in accordance with operating conditions shown in the table ?recommended dc operating conditions.? ac specifications are characterized with v dd = 1.5v, t c = +95 c and a 10pf test load as shown in the figure to the right. table 11. dc power supply loads parameter symbol minimum typical maximum unit notes v dd (1.5v) active operating current i dd 3000 ma 2 ov dd (3.3v) active operating current i odd 30 ma 2 pxv dd (3.3v) active operating current i pdd ---ma2 pxv dd (1.5v) active operating current i pdd - - 1200 ma sv dd (2.5v) active operating current i sdd 285 ma 2 sv dd (1.8v) active operating current i sdd 580 ma 2 axv dd (1.5v) input current i add 33 ma 1, 2 apxv dd (1.5v) input current i apdd 33 ma 1, 2 notes: 1. see ?absolute maximum ratings? on page 58 for filter recommendations. 2. valid only for cpu/plb/opb = 533.33/133.33/66.66 mhz. table 12. clocking specifications symbol parameter min max units sysclk input f c frequency 33.33 83.33 mhz t c period 12 30 ns t cs edge stability (cycle-t o-cycle jitter) ? 0.15 ns t ch high time 40% of nominal period 60% of nominal period ns t cl low time 40% of nominal period 60% of nominal period ns note: input slew rate 1v/ns pll vco f c frequency 600 1333.33 mhz t c period 0.75 1.66 ns output pin 10pf c
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 63 preliminary data sheet figure 4. clock timing waveform spread spectrum clocking care must be taken when using a spread spectrum cloc k generator (sscg) with the ppc440SPE. this controller uses a pll for clock generation inside the chip. the accura cy with which the pll follows the sscg is referred to as tracking skew. the pll bandwidth and phase angle determine how much tracking skew there is between the sscg and the pll for a given frequency deviation and modulation frequency. when using an sscg with the ppc440SPE the following conditions must be met: ? the frequency deviation must not violate the minimum clock cycle time. therefore, when operating the ppc440SPE with one or more internal clocks at their maximum supported frequency, the sscg can only lower the frequency. ? the maximum frequency deviation c annot exceed -1%, and the modulation frequency cannot exceed 40khz. in some cases, on-board ppc440SPE peripherals impose more stringent requirements. ? use the peripheral bus clock for logic that is synchron ous to the peripheral bus since this clock tracks the modulation. ? use the ddr sdram memclkout sinc e it also tracks the modulation. processor clock (cpu clock) f c frequency 400 666.66 mhz t c period 1.5 2.5 ns memclkout f c frequency 200 333.33 mhz t c period 3 5 ns t ch high time 45% of nominal period 55% of nominal period ns opb clock and perclk f c frequency ? 83.33 mhz t c period 12 ? ns mal clock f c frequency 45 83.33 mhz t c period 12 22.2 ns table 12. clocking specifications symbol parameter min max units t cl t ch t c
powerpc 440SPE embedded processor 64 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet ? for pci-x and pci 66 the maximum spread spectrum is -1% modulated between 30khz and 33khz. ? for pci express, the maximum spread spectrum is -0.5%, modulated between 30khz and 33khz. the ports on the two ends of a link must transmit data at a rate th at is within 600 parts per m illion (ppm) of each other at all times. this is specified to allow bit ra te clock sources with a +/- 300 ppm tolerance. notes: 1. the serial port baud rates are synchronous to the modulated clock. the serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. the 1.5% tolerance assumes that the connected device is runni ng at precise baud rates. 2. ethernet operation is unaffected. 3. iic operation is unaffected. important: it is up to the system designer to ensure t hat any sscg used with the ppc440SPE meets the above requirements and does not adversely affect other aspects of the system.
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 65 preliminary data sheet i/o specifications table 13. peripheral interface clock timings parameter min max units notes pcix0clk input frequency (asynchronous mode) ? 133.33 mhz 2 pcix0clk period (asynchronous mode) 7.5 ? ns pcix0clk input high time 40% of nomin al period 60% of nominal period ns pcix0clk input low time 40% of nomin al period 60% of nominal period ns emcmdclk output frequency ? 2.5 mhz emcmdclk period 400 ? ns emcmdclk output high time 160 ? ns emcmdclk output low time 160 ? ns emctxclk input frequency 2.5 25 mhz emctxclk period 40 400 ns emctxclk input high time 35% of nominal period ? ns emctxclk input low time 35% of nominal period ? ns emcrxclk input frequency 2.5 25 mhz emcrxclk period 40 400 ns emcrxclk input high time 35% of nominal period ? ns emcrxclk input low time 35% of nominal period ? ns perclk output frequency (for sync. slaves) ? 83.33 mhz perclk period 12 ? ns perclk output high time 50% of nominal period 66% of nominal period ns perclk output low time 33% of nominal period 50% of nominal period ns uartserclk input frequency ? 1000/(2t opb 1 +2ns) mhz 1 uartserclk period 2t opb +2 ?ns1 uartserclk input high time t opb +1 ?ns1 uartserclk input low time t opb +1 ?ns1 tmrclk input frequency ? 100 mhz tmrclk period 10 ? ns tmrclk input high time 40% of nomin al period 60% of nominal period ns tmrclk input low time 40% of nominal period 60% of nominal period ns notes: 1. t opb is the period in ns of the opb clock. the internal opb clock runs at an integral divisor ratio of the frequency of the plb clock. the maximum opb cl ock frequency is 83.33 mhz. refer to the clocking chapter of the ppc440SPE embedded processor user?s manual for details. 2. when the pci-x interface is used to support a legacy pci interface, the maximum pcixclk frequency is 66.66mhz.
powerpc 440SPE embedded processor 66 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet input/output timing these timing diagrams illustra te the relationship of the timing parameters defined in the i/o specific ation tables that follow. figure 5. input setup and hold waveform figure 6. output delay and hold timing waveform clock t is t ih min min inputs valid valid clock outputs valid t oh min t ov max t ov max t oh min t ov max t oh min float (high-z) high (drive) low (drive)
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 67 preliminary data sheet table 14. i/o specifications?all speeds (sheet 1 of 2) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. 2. pci-x timings are for asynchronous operation up to 133.33mhz. pci-x input setup time requir ement is 1.2ns for 133.33mhz and 1.7ns for 66.66mhz. pci timings (in parentheses) are for a synchronous operation up to 66.66mhz. pci output hold time requirement is 1ns for 66.66mhz and 2ns for 33.33mhz. 3. these are ddr signals that can change on bo th the positive and negative clock transitions. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) pci-x interface pcix0ack64 note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0ad63:00 note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0be7:0 note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0calg0:1 note 2 (2) 0.5(0) n/a n/a n/a n/a pcix0clk 2 pcix0calr0:1 dc dc n/a n/a n/a n/a async pcix0cap note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0clk note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0devsel note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0ecc5:2 n/a n/a 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0frame n/a n/a 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0gnt0 n/a n/a 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0gnt1 note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0gnt2:3 note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0idsel note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0inta note 2 (2) 0.5(0) n/a n/a n/a n/a pcix0clk 2 pcix0irdy note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0m66en note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcixpar note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcixpar64 note 2 (2) 0.5(0) n/a n/a n/a n/a pcix0clk 2 pcix0perr note 2 (2) 0.5(0) n/a n/a n/a n/a pcix0clk 2 pcix0req0 note 2 (2) 0.5(0) n/a n/a n/a n/a pcix0clk 2 pcix0req1:3 n/a n/a n/a n/a n/a n/a pcix0clk 2 pcix0req64 note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0reset note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0serr note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0stop note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0trdy note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 pcix0vc note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0clk 2 ethernet interface emccd - - na na 19.1 8.7 1, async emccrs - - na na 19.1 8.7 1, async emcmdclk na na na na 19.1 8.7 1, async emcmdio - - - - 19.1 8.7 emcmdclk emcrxd0:7 4 1 na na 19.1 8.7 emcrxclk emcrxdv 4 1 na na 19.1 8.7 emcrxclk emcrxerr - - na na 19.1 8.7 emcrxclk emcrxclk - - na na 19.1 8.7 1, async emcrefclk - - na na 19.1 8.7 emctxclk na na na na 19.1 8.7 1, async emcgtxclk na na na na 19.1 8.7 1, async emctxd0:7 na na 15 2 19.1 8.7 emctxclk
powerpc 440SPE embedded processor 68 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet emctxen na na 15 2 19.1 8.7 emctxclk emctxerr na na 15 2 19.1 8.7 emctxclk internal peripheral interface iic0sclk n/a n/a n/a n/a 15.3 10.2 iic0sda - - - - 15.3 10.2 iic0sclk iic1sclk n/a n/a n/a n/a 15.3 10.2 iic1sda - - - - 15.3 10.2 iic0sclk uartserclk n/a n/a n/a n/a 19.1 8.7 uart0_rx - - n/a n/a - - uartserclk uart0_tx n/a n/a - - 19.1 8.7 uartserclk uart0_dcd - - n/a n/a 19.1 8.7 async uart0_dsr - - n/a n/a 19.1 8.7 async uart0_cts - - n/a n/a 19.1 8.7 async uart0_dtr n/a n/a 19.1 8.7 async uart0_ri - - n/a n/a - - async uart0_rts n/a n/a 19.1 8.7 async uart1_rx n/a n/a 19.1 8.7 uartserclk uart1_tx n/a n/a - - 19.1 8.7 uartserclk uart1_dsr/cts - - n/a n/a 19.1 8.7 async uart1_dtr/rts n/a n/a 19.1 8.7 async uart2_rx - - n/a n/a 19.1 8.7 uartserclk uart2_tx n/a n/a - - 19.1 8.7 uartserclk interrupts interface irq0:15 - - - - n/a n/a async jtag interface tdi - - na na na na async tms - - nanananaasync tdo na na - - 19.1 8.7 async tck - - nanananaasync trst - - na na na na async system interface halt - - n/a n/a n/a n/a async gpio00:31 - - - - 19.1 8.7 async sysclk - - n/a n/a n/a n/a na syserr n/a n/a - - 19.1 8.7 async sysreset - - - - n/a n/a async hisrrst - - - - 19.1 8.7 async testen - - n/a n/a n/a n/a async tmrclk - - n/a n/a n/a n/a na trace interface trcclk n/a n/a - - 19.1 8.7 trcbs0:2 - - - - 19.1 8.7 trces0:4 - - - - 19.1 8.7 trcts0:6 - - - - 19.1 8.7 table 14. i/o specifications?all speeds (sheet 2 of 2) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. 2. pci-x timings are for asynchronous operation up to 133.33mhz. pci-x input setup time requir ement is 1.2ns for 133.33mhz and 1.7ns for 66.66mhz. pci timings (in parentheses) are for a synchronous operation up to 66.66mhz. pci output hold time requirement is 1ns for 66.66mhz and 2ns for 33.33mhz. 3. these are ddr signals that can change on bo th the positive and negative clock transitions. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum)
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 69 preliminary data sheet table 15. i/o specifications?667mhz notes: 1. perclk rising edge at package pin with a 10pf load tr ails the internal plb clock by approximately 1.3ns. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) external slave peripheral interface peraddr00:26 n/a 1 6.2 0 19.1 8.7 perclk perbe0:1 - - - - 27.7 12.8 perclk perblast n/a 1 5.7 n/a 19.1 8.7 perclk percs0:2 n/a n/a 5.9 0 19.1 8.7 perclk perdata0:15 1.2 1 6 0 19.1 8.7 perclk peroe n/a n/a 5.8 0 19.1 8.7 perclk perpar0:1 1.7 1 5.7 n/a 19.1 8.7 perclk perready 3.6 1 n/a n/a 19.1 8.7 perclk perr/w n/a 1 5.7 n/a 19.1 8.7 perclk perwe n/a n/a 5.7 0 19.1 8.7 na extreset n/a n/a n/a n/a 19.1 8.7 perclk perclk n/a n/a n/a n/a 19.1 8.7 plb clk pererr 1.2 n/a n/a 19.1 8.7 perclk
powerpc 440SPE embedded processor 70 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet ddr sdram i/o specifications the ddr sdram controller times its oper ation with internal plb clock signals and generates memclkout0 from the plb clock. the plb clock is an internal signal that cannot be directly observed . however memclkout0 is the same frequency as the plb clock signal and is in phase with the plb clock signal. note: memclkout0 can be advanced with respect to the plb clock by means of the sdram0_clktr programming register. in a typical system, users advance memclkout by 90 . this depends on the specific application and requires a thorough understanding of the memory system in general (refer to the ddr sdram controller chapter in the ppc440SPE embedded processor user?s manual ). in the following sections, the label me mclkout0(0) refers to memclkout0 when it has not been phase-shifted, and memclkout0(90) refers to memclkout0 when it has been phase-advanced 90 . advancing memclkout0 by 90 creates a 3/4 cycle setup time and 1/4 cycle hold time for the address and control signals in relation to memclkout0(90). the rising edge of memclkout0(90) a ligns with the first rising edge of the dqs signal. the following ddr data is generated by means of simulation and includes logic, driver, package rlc, and lengths. it is not to be used as a circuit design recommendation. valu es are calculated over best case and worst case processes with speed, temperature, and voltage as follows: best case = fast process, 0c, +1.6v worst case = slow pr ocess, +95c, +1.4v note: in all the following ddr tables and timing diagrams, minimum values are measured under best case conditions and maximum values are measured under worst case conditions. the signals are terminated as indicated in the figure be low for the ddr timing data in the following sections. figure 7. ddr sdram signal termination 10pf 10pf memclkout0 memclkout0 120 50 30pf addr/ctrl/data/dqs v tt = sv dd /2 ppc440SPE note: this diagram illustrates the model of the ddr sdram interface used when generating simulation timing data. it is not a recommended physical circuit design for this interface. an actual interface design will depend on many factors, including the type of memory used and the board layout.
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 71 preliminary data sheet table 16. ddr sdram output driver specifications signal path output current (ma) i/o h (maximum) i/o l (minimum) write data memdata00:07 15.2 15.2 memdata08:15 15.2 15.2 memdata16:23 15.2 15.2 memdata24:31 15.2 15.2 memdata32:39 15.2 15.2 memdata40:47 15.2 15.2 memdata48:55 15.2 15.2 memdata56:63 15.2 15.2 ecc0:7 15.2 15.2 dm0:8 15.2 15.2 memclkout0 15.2 15.2 memaddr00:12 15.2 15.2 ba0:1 15.2 15.2 ras 15.2 15.2 cas 15.2 15.2 we 15.2 15.2 banksel0:3 15.2 15.2 clken0:3 15.2 15.2 dqs0:8 15.2 15.2
powerpc 440SPE embedded processor 72 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet ddr sdram write operation the following timing chart shows the relationship between the signals involved in a ddr write operation. figure 8. ddr sdram write cycle timing ddr sdram read and write i/o timing?t sa and t ha note 1: clock speed is 333 mhz. t sa and t ha are referenced to memclkout. note 2: memory clock signal is shifted by 90 from the internal clock. table 17. ddr sdram read and write i/o timing?t sa and t ha signal name t sa (ns) t ha (ns) minimum minimum memaddr00:12 1.32 1.2 ba0:1 1.15 1.49 banksel0:3 1.12 1.52 clken0:3 1.29 1.45 cas 1.24 1.14 ras 1.29 1.48 we 1.35 1.43 dqs memdata plb clk memclkout addr/cmd t sa t ha t ds t sd t hd t sd t hd t sa = setup time for address and command signals to memclkout t ha = hold time for address and command signals from memclkout t ds = delay from rising/falling edge of clock to the rising/falling edge of dqs t sd = setup time for data signals (minimum time data is valid before rising/falling edge of dsq) t hd = hold time for data signals (minimum time data is valid after rising/falling edge of dsq)
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 73 preliminary data sheet ddr sdram clock to write dqs timing?t ds note 1: all of the dqs signals are referenced to memclkout. note 2: clock speed is 333 mhz. note 3: the tds values in the table include 1.5 3ns cycle at 333 mhz (3 ns 1.5 = 4.5 ns). note 4: to obtain adjusted values for lower clock frequencies, subtract 4 ns from the values in the following table and add 1.5 of the cycle time for the lower clock frequency (t ds - 4.5 + 1.5 t cyc ). ddr sdram write data to dqs timing?t sd and t hd note 1: t sd and t hd are measured under worst-case conditions. note 2: clock speed for the values in the following table is 333 mhz. table 18. ddr sdram clock to write dqs timing?t ds signal name t ds (ns) minimum maximum dqs0 4.76 5.07 dqs1 4.78 5.09 dqs2 4.78 5.10 dqs3 4.76 5.07 dqs4 4.79 5.11 dqs5 4.80 5.13 dqs6 4.81 5.11 dqs7 4.79 5.11 dqs8 4.77 5.07 table 19. ddr sdram write data to dqs timing?t sd and t hd signal name reference signal t sd (ns) t hd (ns) memdata00:07, dm0 dqs0 0.58 0.64 memdata08:15, dm1 dqs1 0.62 0.55 memdata16:23, dm2 dqs2 0.62 0.60 memdata24:31, dm3 dqs3 0.63 0.57 memdata32:39, dm4 dqs4 0.68 0.54 memdata40:47, dm5 dqs5 0.67 0.52 memdata48:55, dm6 dqs6 0.62 0.61 memdata56:63, dm7 dqs7 0.65 0.55 ecc0:7, dm8 dqs8 0.63 0.61
powerpc 440SPE embedded processor 74 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet ddr sdram read operation the read of the incoming da ta from the sdram is done on the rising and falling edges of the differential dqs signal. the data must be centered to these edges for correct operation. the ppc440SPE can delay with very fine granula rity the dqs through the programming of the mcif0_rodc[rqfd] register field. ddr sdram memclkout0 and read clock delay in order to accommodate timing variations introduced by the system designs using this chip, the three-stage data path shown below is used to eliminat e metastability and allow dat a sampling to be adjusted for minimum latency. the data are stored in the 8 flip flops of the stage 1, such that it can be transferred later within a 8x period. figure 9. ddr sdram read data path plb bus dq mcif0_rqdc[rqfd] programmed delay package mux read dqs c d ff: flip-flop q2 dqs (diff) ddr 1x clock mux data (x64) (x64) read fifo plb 1x clock stage 2 stage 1 stage 3 ff plb bus [0:63] [64:127] dqs rising dqs falling q3 0 6 4 2 (x64) coarse delay cycles driver rec memdcfdbkd memdcfdbkr ext feedback read start feedback data capture window ddr 1x clock mcif0_rdcc[rdss] mcif0_rfdc[rffd] mcif0_rfdc[rfos] stage 2 store oversampling dqs aligned cas lat delay feedback signal gen fine delay t1 t2 t3 t4 fine delay ff ff 7 5 3 1 1 0 7 edge sync edge sync upper lower signals pins ff q2_ovs ff fbk signal delay +1 compare ddr 1x clock oversampling clock read latency adjust circuit c d ff ff adjust
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 75 preliminary data sheet in the following examples, the data strobes (dqs) and the data are shown to be coincident. there is actually a slight skew as specified by the sdram specifications, an d there can be additional skew due to loading and signal routing. it is recommended that the signal length for all of the eight dqs signals be matched. figure 10. ddr sdram memory data and dqs table 20. ddr sdram i/o read timing?t sd and t hd notes: 1. t sd and t hd are measured under worst case conditions. 2. clock speed for the values in the table is 333.33mhz. 3. the time values in the table include 1/ 4 of a cycle at 166mhz (3ns x 0.25 = 0.75 ns). 4. to obtain adjusted t sd and t hd values for lower clock frequencies, subtract 0.75 ns from the values in the table and add 1/4 of the cycle time for the lo wer clock frequency (e.g., t sd - 0.75 + 0.25t cyc ). signal names reference signal read data vs dqs set up t sd (ns) read data vs dqs hold t hd (ns) memdata00:07 dqs0 0.00 1.00 memdata08:15 dqs1 0.00 1.00 memdata16:23 dqs2 0.00 1.00 memdata24:31 dqs3 0.00 1.00 memdata32:39 dqs4 0.00 1.00 memdata40:47 dqs5 0.00 1.00 memdata48:55 dqs6 0.00 1.00 memdata56:63 dqs7 0.00 1.00 ecc0:7 dqs8 0.00 1.00 dqs memdata t sd t hd
powerpc 440SPE embedded processor 76 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet the following example shows the timing relationship betw een sdram ddr data at the input pin and the store of the data in stage 1. figure 11. ddr sdram read cycle timing?example dqs at plb 1x clock data at pin d0 d2 high low feedback d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 data out stage 2 d1 d3 ddr 1x clock ddr 2x clock memclk (diff.) data out stage 1 (0) delayed dqs data out stage 1 (2) data out stage 1 (1) output 1x ddr clk cycle memcntl pin valid store 1st data in stage 2 t1 t2 t3 t4 oversampling guard band
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 77 preliminary data sheet initialization the ppc440SPE provides the option for setting initial parame ters based on default values or by reading them from a serial ?bootstrap? rom attached to the iic0 bus. these options are defined by strappi ng on three external pins (see ?strapping? below). strapping while the sysreset input pin is low (system reset), the state of cert ain i/o pins is read to enable certain default initial conditions prior to ppc440SPE start-up. the actual capture instant is the nearest sysclk edge before the deassertion of reset. these pins must be strapped usin g external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. they are used for strap functions only during reset. following reset they are used for normal functions. the following table lists the strapping pins al ong with their functions and strapping options: serial bootstrap rom during reset, if the serial device is enabled, initial conditions can be read fr om a rom connected to the iic0 port. in this case, at the de-assertion of sysreset, the ppc440SPE sequentially reads up to 32 bytes from the rom device on the iic0 port and sets the sdr0_sds tp0 - sdr0_sdstp7 registers accordingly. the initialization settings and their default values are covered in detail in the ppc440SPE embedded processor user?s manual . table 21. strapping pin assignments function option pin strapping bit 0 h13 (uart0_dcd ) bit 1 c12 (uart0_dsr ) bit2 b08 (uart0_cts ) serial bootstrap rom is disabled (bit 0 off). refer to the iic bootstrap controller chapter in the ppc440SPE embedded processor user?s manual for details. boot from ebc 0 0 boot from pci 0 1 serial bootstrap rom is enabled (bit 0 on). the options being selected are the iic0 slave address that responds with strapping data and reading 128 bits from the bootstrap rom. 0x54 1 0 0 0x50 1 1 0 serial bootstrap rom is enabled (bit 0 on). the options being selected are the iic0 slave address that responds with strapping data and reading 256 bits from the bootstrap rom. 0x54 1 0 1 0x50 1 1 1
powerpc 440SPE embedded processor 78 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet document revision history revision date description 1.23 sept 21, 2006 updated recommended dc operating conditions table. 1.22 sept 12, 2006 updated processor clock va lues in clocking specifications table. 1.21 june 27, 2006 updated recommended dc op conditions and signal functional description tables for pci-x ddr mode 2. 1.20 june 14, 2006 updated signal lists. corrected reference to pcix 0cap in signal functiona l description table. added reference to note 6 for uart0_cts regist er in signal functio nal description table. 1.19 may 23, 2006 fixed doc issue for peroe signal in signal func tional description table. fixed doc issue for uartserclk signal throughout doc ument. fixed doc issue for psro1 signal in signal functional description table. updated cloc king specifications table and serial bootstrap rom paragraph. 1.18 may 1, 2006 updated ordering and pvr information, and core package graphic in figure 3. added raid acceleration section to features, descri ption, and functional details sections. 1.17 april 6, 2006 additional update to ordering and pvr information. gjg 1.16 march 8, 2006 updated ordering and pvr information, part number list, and package diagram. gjg 1.15 march 7, 2006 removed dma statement from serial port feature statement. removed reference to notes from perblast entry in signal functional description table. gjg 1.14 march 6, 2006 updated description of on-chip sram/l2 cache in introduction. gjg 1.13 january 9, 2006 updated signal function description table per jb, updated mailing address and copyright date in disclaimer. gjg 1.12 november 15, 2005 clarified informati on about ddr sdram i/o specifications. gjg 1.11 october 26, 2005 corrected upper limit of allowable case tem perature, documented reserved signal pins, added bookmarks for sign al lists. gjg 1.10 october 17, 2005 restored multiplexed signal information to t he ?signals listed alphabetic ally? table. applied corrections to the table from gb. gjg 1.09 july 12, 2005 updated leakage current info, case te mp range, ddr sdram signal termination graphic. gjg 1.08 may 23, 2005 update write timing diagrams. gjg 1.07 may 20, 2005 updated system memory addres s map. corrected functional block diagram. gjg 1.06 mar 10, 2005 removed text for unsupported cola component. gjg 1.05 feb 15, 2005 removed references to unsupported co la serial interface. reformatted lof, lot to comply with amcc style. gjg 1.04 dec 21, 2004 update max case temp in recommended dc op conditions table to match ordering and pvr information table. gjg 1.03 dec 20, 2004 update ordering and pvr info, pci express features info, ddr sdram read data path and read cycle timing example, memory map. gjg 1.02 sept 21, 2004 pci-express rx tx pin assignment changes. gjg 1.01 sept 13, 2004 converted to amcc forma t, corrected tables, graphics as needed. gjg 0.5 sept 10, 2004 renamed 440SPE, added mux table, vdda 2.5v (in progress) 0.4 aug 02, 2004 miscellaneous technical additi ons, pn and corrections from support. 0.3 july 18, 2004 correct toc, lof, lot, broken cross-references. 0.2 june 25, 2004 add alphabetic list, update sys mem address map. 0.1 june 18, 2004 create initial data sheet.
powerpc 440SPE embedded processor revision 1.23 - sept 21, 2006 amcc proprietary 79 preliminary data sheet
powerpc 440SPE embedded processor 80 amcc proprietary revision 1.23 - sept 21, 2006 preliminary data sheet applied micro circuits corporation 215 moffett park dr., sunnyvale, ca 94089 phone: (858) 450-9333 ? (800) 755-2622 ? fax: (858) 450-9885 http://www.amcc.com amcc reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially co mply with the latest available datasheet. please consult amcc?s term and condi tions of sale for its warranties and ot her terms, conditions and limitations. amcc may discontinue any semiconductor product or service wi thout notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the info rmation is current. amcc does not assume any lia - bility arising out of the application or use of any product or circuit described herein, neither does it convey any license und er its patent rights nor the rights of others. amcc reserves the ri ght to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed , intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. amcc is a registered trademark of appli ed micro circuits corporation. copyright ? 2006 applied micro circuits corporation.

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